Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.
1. A method of making a semiconductor device, comprising:
providing a substrate including a first interconnect site and a second interconnect site;
depositing a conductive material self-confined with respect to and contacting a top surface and side surfaces of the first interconnect site and second interconnect site immediately adjacent to a surface of the substrate by surface tension of a wettable state of the conductive material absent mask material between the first interconnect site and second interconnect site; and
forming an insulating layer around the first interconnect site and second interconnect site.
2. The method of claim 1 , further including:
providing a semiconductor die including a third interconnect site; and
disposing the semiconductor die over the substrate with the third interconnect site aligned with the conductive material self-confined over the first interconnect site.
3. The method of claim 2 , further including depositing an encapsulant between the substrate and semiconductor die.
4. The method of claim 1 , further including selecting a volume of the conductive material deposited over the first interconnect site to maintain self-confinement of the conductive material.
5. The method of claim 1 , wherein the conductive material includes a fusible portion and non-fusible portion.
6. The method of claim 1 , wherein a pitch between the first interconnect site and second interconnect site is given as P=D/2+PLT+W/2, where D is a diameter of the conductive material, PLT is die placement tolerance, and W is a width of the first interconnect site and second interconnect site.
7. A method of making a semiconductor device, comprising:
providing a first substrate including a first interconnect site and second interconnect site; and
depositing a conductive material self-confined with respect to a top surface and side surfaces of the first interconnect site immediately adjacent to a surface of the first substrate by surface tension of the conductive material without mask material between the first interconnect site and second interconnect site.
8. The method of claim 7 , further including:
providing a second substrate including a third interconnect site; and
disposing the second substrate over the first substrate with the third interconnect site aligned with the conductive material self-confined over the first interconnect site.
9. The method of claim 8 , further including depositing an encapsulant between the first substrate and second substrate.
10. The method of claim 7 , further including immersing the conductive material in a flux solution.
11. The method of claim 7 , further including selecting a volume of the conductive material deposited over the first interconnect site to maintain self-confinement of the conductive material.
12. The method of claim 7 , wherein the conductive material includes a fusible portion and non-fusible portion.
13. The method of claim 7 , further including forming an insulating layer around the first interconnect site.
14. A semiconductor device, comprising:
a first substrate including a first interconnect site and a second interconnect site;
a conductive material self-confined with respect to and contacting a top surface and side surfaces of the first interconnect site and second interconnect site immediately adjacent to a surface of the first substrate by surface tension of a wettable state of the conductive material; and
an insulating layer formed around the first interconnect site and second interconnect site.
15. The semiconductor device of claim 14 , further including a second substrate including a third interconnect site, wherein the second substrate is disposed over the first substrate with the third interconnect site aligned with the conductive material self-confined over the first interconnect site.
16. The semiconductor device of claim 15 , further including an encapsulant deposited between the first substrate and second substrate.
17. The semiconductor device of claim 14 , wherein a volume of the conductive material deposited over the first interconnect site maintains self-confinement of the conductive material.
18. The semiconductor device of claim 14 , wherein the conductive material includes a fusible portion and non-fusible portion.
19. A semiconductor device, comprising:
a first substrate including a first interconnect site and second interconnect site; and
a conductive material self-confined with respect to a top surface and side surfaces of the first interconnect site by surface tension of the conductive material without mask material between the first interconnect site and second interconnect site.
20. The semiconductor device of claim 19 , further including a second substrate including a third interconnect site, wherein the second substrate is disposed over the first substrate with the third interconnect site aligned with the conductive material self-confined over the first interconnect site.
21. The semiconductor device of claim 20 , further including an encapsulant deposited between the first substrate and second substrate.
22. The semiconductor device of claim 19 , further including a flux solution deposited over the conductive material.
23. The semiconductor device of claim 19 , wherein a volume of the conductive material deposited over the first interconnect site maintains self-confinement of the conductive material.
24. The semiconductor device of claim 19 , further including an insulating layer formed around the first interconnect site.