Flip chip interconnection having narrow interconnection sites on the substrate
View Patent ↗A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.
1. A method of making a semiconductor device, comprising:
forming a plurality of contact pads over a surface of a semiconductor die;
forming a plurality of conductive traces formed over a surface of a substrate, the conductive traces having an interconnect site; and
forming a plurality of composite bumps between the contact pads and interconnect sites, wherein a width of the interconnect site is greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads formed over the semiconductor die and a length of the interconnect site is equal to or greater than the width of the contact interface.
2. The method of claim 1 , wherein the conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
3. The method of claim 1 , wherein the width of the interconnect site is substantially equal to a width of the conductive traces.
4. The method of claim 1 , wherein the width of the interconnect site is 120% of a width of the conductive traces.
5. The method of claim 1 , wherein the interconnect sites have generally rectangular, elongated, or rounded shape.
6. The method of claim 1 , wherein the bumps include a non-fusible portion adjacent to the contact pad and fusible portion adjacent to the interconnect site.
7. A method of making a semiconductor device, comprising:
forming a plurality of contact pads formed over a surface of a semiconductor die;
forming a plurality of conductive traces over a surface of a substrate, the conductive traces having an interconnect site; and
forming a composite interconnect structure having fusible and non-fusible portions between the contact pads and interconnect sites, wherein the conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate, the conductive trace has a length greater than a width of the contact pad, and a width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
8. The method of claim 7 , wherein the width of the interconnect site is greater than 20% and less than 80% of a width of a contact interface between the interconnect structure and contact pad.
9. The method of claim 7 , wherein the width of the interconnect site is substantially equal to a width of the conductive traces.
10. The method of claim 7 , wherein the width of the interconnect site is 120% of a width of the conductive traces.
11. The method of claim 7 , wherein the interconnect sites have generally rectangular, elongated, or rounded shape.
12. The method of claim 7 , wherein the interconnect structure includes a bump.
13. The method of claim 12 , wherein the bump includes a non-fusible portion adjacent to the contact pad and fusible portion adjacent to the interconnect site.
14. A method of making a semiconductor device, comprising:
forming a plurality of contact pads formed over a surface of a semiconductor die;
forming a plurality of conductive traces formed over a surface of a substrate, the conductive traces having an interconnect site and a length greater than a width of the contact pad; and
forming an interconnect structure between the contact pads and interconnect sites, wherein a width of the interconnect site is substantially equal to a width of the conductive traces.
15. The method of claim 14 , wherein the width of the interconnect site is 120% of the width of the conductive traces.
16. The method of claim 14 , wherein the conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
17. The method of claim 14 , wherein the width of the interconnect site is greater than 20% and less than 80% of a width of a contact interface between the interconnect structure and contact pad.
18. The method of claim 14 , wherein the interconnect sites have generally rectangular, elongated, or rounded shape.
19. The method of claim 14 , wherein the interconnect structure includes a bump.
20. The method of claim 19 , wherein the bump includes a non-fusible portion adjacent to the contact pad and fusible portion adjacent to the interconnect site.
21. A semiconductor device, comprising:
a semiconductor die having a plurality of contact pads formed over a surface of the semiconductor die;
a substrate having a plurality of conductive traces formed over a surface of the substrate, the conductive traces having an interconnect site and a length greater than a width of the contact pad; and
an interconnect structure formed between the contact pads and interconnect sites, wherein a width of the interconnect site is substantially equal to a width of the conductive traces.
22. The semiconductor device of claim 21 , wherein the width of the interconnect site is 120% of the width of the conductive traces.
23. The semiconductor device of claim 21 , wherein the conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
24. The semiconductor device of claim 21 , wherein the width of the interconnect site is greater than 20% and less than 80% of a width of a contact interface between the interconnect structure and contact pad.
25. The semiconductor device of claim 21 , wherein the interconnect structure includes a non-fusible portion adjacent to the contact pad and fusible portion adjacent to the interconnect site.