Methods of making memory devices with programmable impedance elements and vertically formed access devices

1. A method, comprising:

forming a plurality of access transistors, including

forming second semiconductor regions over an integrated circuit substrate that are doped to a second conductivity type, the second semiconductor regions being over and in contact with first semiconductor regions doped to a first conductivity type, and

forming third semiconductor regions doped to the first conductivity type in contact with the second semiconductor regions;

forming a plurality of conductive structures, over and in contact with the third semiconductor regions; and

forming programmable impedance memory cells over and in contact with the conductive structures.

2. The method of claim 1 , wherein:

forming the second semiconductor regions includes forming a semiconductor layer in contact with an integrated circuit substrate that includes the first semiconductor regions.

3. The method of claim 1 , wherein:

forming the second semiconductor regions includes forming first semiconductor structures doped to the second conductivity type; and

forming the third semiconductor regions includes doping a portion of the first semiconductor structures to the first conductivity type.

4. The method of claim 3 , further including:

forming the first semiconductor structures over the integrated circuit substrate.

5. The method of claim 4 , wherein:

forming the first semiconductor structures includes

depositing a first semiconductor layer, and

patterning the first semiconductor layer into the first semiconductor structures, the first semiconductor structures being first lines disposed in a first direction over an integrated circuit substrate.

6. The method of claim 5 , wherein:

the second semiconductor regions are second lines disposed in a second direction different than the first direction.

7. The method of claim 6 , wherein:

the first direction is substantially perpendicular to the second direction.

8. The method of claim 1 , wherein:

forming the programmable impedance memory cells includes

forming a first electrode layer with a conductive connection to the emitter/collector terminals of the access transistors,

forming the at least one memory layer over the first electrode layer, and

forming a second electrode layer over the memory layer, wherein

the at least one memory layer undergoes the oxidation-reduction reaction in response to the applied voltage or current between the first electrode layer and the second electrode layer.

9. The method of claim 8 , wherein:

the memory layer includes at least one ion that is ion conductible in the memory layer in response to the applied voltage or current.