Gate cut with high selectivity to preserve interlevel dielectric layer
View Patent ↗A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
1. A method for preserving interlevel dielectric in a gate cut region, comprising:
forming a liner in a recess on top of a recessed dielectric fill-in a device region and in a cut region by conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill, and planarizing the liner to remove the liner over the gate structures, the liner including a material to provide etch selectivity to protect the recessed dielectric fill;
recessing gate structures in the cut region to form a gate recess using the liner to protect the recessed dielectric fill from being etched;
removing a gate material from within the gate structures using the liner to protect the recessed dielectric fill from being etched; and
forming a dielectric gap fill to replace the gate material and to fill the gate recess in the cut region.
2. The method as recited in claim 1 , wherein forming the liner includes: forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.
3. The method as recited in claim 1 , wherein forming the liner includes: forming the liner from TiN.
4. The method as recited in claim 1 , wherein recessing the gate structures in the cut region includes patterning a mask layer to protect the device region and etching a cap layer of the gate structure in the cut region.
5. The method as recited in claim 1 , wherein removing the gate material includes removing a dummy gate.
6. The method as recited in claim 1 , wherein removing the gate material includes removing a gate first structure.
7. The method as recited in claim 1 , wherein forming the dielectric gap fill includes forming the dielectric gap fill between spacers formed in the gate structure.
8. The method as recited in claim 1 , further comprising:
forming gate structures in the device region and the cut region; and
forming source and drain regions in the device region.
9. The method as recited in claim 8 , wherein forming the source and drain regions in the device region includes epitaxially growing the source and drain regions between the gate structures.
10. The method as recited in claim 1 , further comprising:
depositing and planarizing a dielectric fill to fill in gaps between the gate structures in the device region and the cut region; and
recessing the dielectric fill to form the recessed dielectric fill and to expose a cap layer at a top portion of the gate structures.
11. A method for preserving interlevel dielectric in a gate cut region, comprising:
forming a liner in a recess on top of a recessed dielectric fill-in a device region and in a cut region, the liner including a material to provide etch selectivity to protect the recessed dielectric fill;
recessing gate structures in the cut region to form a gate recess using the liner to protect the recessed dielectric fill from being etched by patterning a mask layer to protect the device region and etching a cap layer of the gate structure in the cut region;
removing a gate material from within the gate structures using the liner to protect the recessed dielectric fill from being etched; and
forming a dielectric gap fill to replace the gate material and to fill the gate recess in the cut region.
12. The method as recited in claim 11 , wherein forming the liner includes: conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill; and
planarizing the liner to remove the liner over the gate structures.
13. The method as recited in claim 11 , wherein forming the liner includes: forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.
14. The method as recited in claim 11 , wherein forming the liner includes: forming the liner from TiN.
15. The method as recited in claim 11 , wherein removing the gate material includes removing a dummy gate.
16. The method as recited in claim 11 , wherein removing the gate material includes removing a gate first structure.
17. The method as recited in claim 11 , wherein forming the dielectric gap fill includes forming the dielectric gap fill between spacers formed in the gate structure.
18. The method as recited in claim 11 , further comprising:
forming gate structures in the device region and the cut region; and
forming source and drain regions in the device region.
19. The method as recited in claim 18 , wherein forming the source and drain regions in the device region includes epitaxially growing the source and drain regions between the gate structures.
20. The method as recited in claim 11 , further comprising:
depositing and planarizing a dielectric fill to fill in gaps between the gate structures in the device region and the cut region; and
recessing the dielectric fill to form the recessed dielectric fill and to expose a cap layer at a top portion of the gate structures.