IP Library Granted Patent US 9,741,895
Granted Patent B2
US 9,741,895 · App. 15/159,235 · Granted Aug 22, 2017

Removal of 3D semiconductor structures by dry etching

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Quick Facts
Patent No.
US 9,741,895
App. No.
15/159,235
Granted
Aug 22, 2017
Kind
B2
Abstract

Various embodiments include methods of fabricating a semiconductor device that include providing a plurality of nanostructures extending away from a support, forming a flowable material layer between the nanostructures, forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of nanostructures, such that a second portion of the flowable material and a second portion of the plurality of nanostructures are not located under the patterned mask and etching the second portion of the flowable material and the second portion of the plurality of nanostructures to remove the second portion of the flowable material and the second portion of the plurality of nanostructures to leave the first portion of the flowable material and the first portion of the plurality of nanostructures unetched.

Claims (27)

1. An etching method comprising:

providing a support containing a semiconductor buffer layer;

forming a dielectric masking layer on the semiconductor buffer layer;

forming openings in the dielectric masking layer to expose the semiconductor buffer layer;

growing a plurality of semiconductor nanostructures extending away from the support through the openings in the dielectric masking layer and in contact with the semiconductor buffer layer exposed in the openings, such that the plurality of semiconductor nanostructures extend above a top surface of the dielectric masking layer;

forming a flowable material layer between the semiconductor nanostructures and over a top surface of the dielectric masking layer to cover an entire top surface of the dielectric masking layer;

forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of semiconductor nanostructures, wherein the patterned mask is vertically spaced from the dielectric masking layer at least by a bottom portion of the flowable material that overlies the dielectric masking layer, such that a second portion of the flowable material and a second portion of the plurality of semiconductor nanostructures are not located under the patterned mask; and

etching the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to remove the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to leave the first portion of the flowable material and the first portion of the plurality of semiconductor nanostructures unetched.

2. The method of claim 1 , further comprising selectively removing at least a part of the first portion of the flowable material after the step of etching to leave the first portion of the plurality of semiconductor nanostructures over the support.

3. The method of claim 1 , wherein forming the patterned mask comprises depositing a photoresist layer over the flowable material layer and pattering the photoresist.

4. The method of claim 1 , wherein the step of etching comprises etching the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to remove the second portion of the flowable material and the second portion of the plurality of semiconductor nanostructures to leave the patterned mask, the first portion of the flowable material and the first portion of the plurality of semiconductor nanostructures unetched.

5. The method of claim 1 , further comprising etching the first portion of the flowable material to reduce a height of the first portion of the flowable material between the first portion of the plurality of semiconductor nanostructures.

6. The method of claim 1 , wherein the flowable material comprises a spin on glass or a photoresist.

7. The method of claim 1 , wherein:

the flowable material layer comprises a photoresist material layer; and

the method comprises exposing a region of an upper portion of the photoresist material layer to radiation while not exposing another region of the upper portion of the photoresist material layer and a lower portion of the photoresist material layer, and removing the exposed region of the upper portion of the photoresist material layer, wherein the unexposed portion of the photoresist material layer constitutes the patterned mask.

8. The method of claim 7 , further comprising etching remaining portions of the photoresist material layer by an anisotropic dry etching process to remove regions of the lower portion of the photoresist material layer that are not covered by the patterned mask concurrently with removal of the patterned mask.

9. The method of claim 7 , wherein:

regions of the lower portion of the photoresist material layer that are not covered by the patterned mask includes the second portion of the flowable material; and

the method comprises etching the second portion of the flowable material concurrently with removal of the patterned mask.

10. The method of claim 9 , wherein the second portion of the flowable material and the patterned mask are removed by an anisotropic dry etching process.

11. The method of claim 1 , wherein:

the flowable material layer comprises a spin on glass; and

the patterned mask comprises a photoresist layer that is applied directly on a top surface of the flowable material layer and is subsequently lithographically patterned.

12. The method of claim 11 , wherein:

regions of the flowable material layer that are not covered by the patterned mask include the second portion of the flowable material; and

the method comprises etching the second portion of the flowable material employing the patterned mask as an etch mask.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2024
From: GLO TECHNOLOGIES LLC
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068297/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2023
From: SYSONAN, INC.
To: GLO TECHNOLOGIES LLC
Reel/Frame 065178/0210 →
CHANGE OF NAME Recorded Oct 5, 2023
From: NANOSYS, INC.
To: SYSONAN, INC.
Reel/Frame 065156/0416 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT RECORDED AT REEL 059569 / FRAME 0840 Recorded Sep 7, 2023
From: FORTRESS CREDIT CORP.,
To: NANOSYS, INC.
Reel/Frame 064836/0263 →
SECURITY INTEREST Recorded Apr 1, 2022
From: NANOSYS, INC.
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 059569/0840 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 13, 2021
From: GLO AB
To: NANOSYS, INC.
Reel/Frame 057184/0564 →
RELEASE OF SECURITY INTEREST Recorded Apr 12, 2021
From: HERCULES CAPITAL, INC.
To: GLO AB
Reel/Frame 057210/0690 →
SECURITY INTEREST Recorded Jan 23, 2019
From: GLO AB
To: HERCULES CAPITAL INC.
Reel/Frame 048110/0063 →
ASSIGNMENT OF IP SECURITY AGREEMENT Recorded Dec 12, 2018
From: GLO AB
To: HERCULES CAPITAL, INC., AS ADMINISTRATIVE AGENT
Reel/Frame 049042/0527 →