Wafer structure for electronic integrated circuit manufacturing
View Patent ↗A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
1. A method of forming a wafer structure comprising:
forming a first region having at least one major surface, a thickness, and a conductivity profile of a first conductivity type substantially perpendicular to said at least one major surface;
forming a second region having a thickness, and a second conductivity profile of the first conductivity type of said first region, such second conductivity profile being substantially different than the conductivity profile of said first region, such that said second region is in electrical contact with said first region opposite the major surface of said first region;
forming an interface region formed between said first region and said second region; and
placing impurity sites in at least one of said first region, said second region, and said interface region, by bombardment of high energy monoenergetic neutron irradiation, and
wherein said first region, said second region, and said interface region comprise the same polarity semiconductor material.
2. A method of forming a wafer structure comprising:
forming a first region in a device wafer having at least one major surface, a thickness, and a conductivity profile of a first conductivity type substantially perpendicular to said at least one major surface;
forming a second region in a handle wafer having a thickness, and a second conductivity profile of the first conductivity type of said first region, such second conductivity profile being substantially different than the conductivity profile of said first region, such that said second region is in electrical contact with said first
region opposite the major surface of said first region; bonding together said device and handle wafers; forming an interface region formed between said first region and said second region; and placing impurity sites in at least one of said first region, said second region, and said interface region by high-energy monoenergetic neutron bombardments, and wherein said first region, said second region, and said interface region comprise the same polarity semiconductor material.
3. The method of claim 2 further comprising grinding said bonded device and handle wafers, the structure having been treated with high-energy monoenergetic neutron bombardments.
4. The method of claim 2 wherein the wafer structure is treated with a high-energy monoenergetic neutron source obtained from a deuterium-tritium reaction.
5. The method of claim 2 wherein the wafer structure is treated with a high-energy monoenergetic neutron source obtained from a deuterium-deuterium reaction.
6. The method of claim 2 wherein the wafer structure is treated with a high-energy monoenergetic neutron source obtained from a secondary reaction of charged particles.
7. The method of claim 2 wherein the wafer structure is treated with a high-energy monoenergetic neutron source obtained from a secondary reaction of protons.