Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

1. A method of forming an integrated circuit structure, the method comprising:

providing a substrate having a front side and a back side, the substrate including:

a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate, and

a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer;

etching the back side of the substrate to expose the insulating layer of TSV on the back side of the substrate without exposing the DT capacitor, wherein the etching of the back side of the substrate includes exposing a portion of the insulating layer that is disposed along a sidewall of the TSV; and

forming a first dielectric layer covering the exposed insulating layer of TSV on the back side of the substrate and extending away from the front side of the substrate, a portion of the first dielectric layer being laterally adjacent to the portion of the insulating layer that is disposed along the sidewall of the TSV such that the portion of insulating layer is disposed between the sidewall of the TSV and the portion of the first dielectric layer.

2. The method of claim 1 , further comprising:

planarizing the first dielectric layer, after the forming of the first dielectric layer, to a surface of the insulating layer of the TSV that is farthest from the front side of the substrate.

3. The method of claim 2 , further comprising:

after the planarizing of the first dielectric layer, removing a portion of the insulating layer of the TSV that is farthest from the front side of the substrate to expose a portion of the liner layer of the TSV; and

forming a conductive pad over the back side of the substrate extending away from the front side of the substrate, the conductive pad covering a portion of the first dielectric layer and the first liner layer of the TSV such that the conductive pad is in electrical connection with the TSV.

4. The method of claim 3 , further comprising:

forming a second dielectric layer over the back side of the substrate extending away from the front side of the substrate, the second dielectric layer covering the conductive pad and at least a portion of the first dielectric layer.

5. The method of claim 4 , further comprising:

forming a connection within the second dielectric layer connected to the conductive pad.

6. The method of claim 1 , wherein the forming of the first dielectric layer includes forming a polymer.

7. The method of claim 1 , further comprising:

forming a wire adjacent to and separated from the TSV during the forming of the first dielectric layer.

8. The method of claim 7 , further comprising:

forming a connection extending from the wire away from the front side of the substrate to a surface of the first dielectric layer that is farthest from the front side of the substrate;

removing a portion of the insulating layer of the TSV that is farthest from the front side of the substrate to expose a portion of the liner layer of the TSV; and

forming a conductive pad over the TSV, the connection, and at least a portion of the first dielectric layer such that the wire is electrically connected to the TSV by the connection and the conductive pad.

9. The method of claim 8 , wherein the etching of the back side of the substrate includes etching the back side of the substrate to expose the DT capacitor on the back side of the substrate.

10. A method of forming an integrated circuit structure, the method comprising:

providing a substrate having a front side and a back side, the substrate including:

a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate, and

a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer;

etching the back side of the substrate to expose the TSV on the back side of the substrate;

forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate;

planarizing the first dielectric layer to a surface of the insulating layer of the TSV that is farthest from the front side of the substrate;

removing a portion of the insulating layer of the TSV that is farthest from the front side of the substrate to expose a portion of the liner layer of the TSV; and

forming a conductive pad over the back side of the substrate extending away from the front side of the substrate, the conductive pad covering a portion of the first dielectric layer and the liner layer of the TSV such that the conductive pad is in electrical connection with the TSV.

11. The method of claim 10 , further comprising:

forming a second dielectric layer over the back side of the substrate extending away from the front side of the substrate, the second dielectric layer covering the conductive pad and at least a portion of the first dielectric layer.

12. The method of claim 11 , further comprising:

forming a connection within the second dielectric layer connected to the conductive pad.

13. The method of claim 10 , wherein the forming of the first dielectric layer includes forming a polymer.

14. The method of claim 10 , further comprising:

forming a wire adjacent to and separated from the TSV during the forming of the first dielectric layer.

15. The method of claim 14 , further comprising:

forming a connection extending from the wire away from the front side of the substrate to a surface of the first dielectric layer that is farthest from the front side of the substrate;

removing a portion of the insulating layer of the TSV that is farthest from the front side of the substrate to expose a portion of the liner layer of the TSV; and

forming a conductive pad over the TSV, the connection, and at least a portion of the first dielectric layer such that the wire is electrically connected to the TSV by the connection and the conductive pad.

16. The method of claim 15 , wherein the etching of the back side of the substrate includes etching the back side of the substrate to expose the DT capacitor on the back side of the substrate.

17. A method of forming an integrated circuit structure, the method comprising:

providing a substrate having a front side and a back side, the substrate including:

a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate, and

a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer;

etching the back side of the substrate to expose the TSV on the back side of the substrate;

forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate; and

forming a wire adjacent to and separated from the TSV during the forming of the first dielectric layer.

18. The method of claim 17 , further comprising:

forming a connection extending from the wire away from the front side of the substrate to a surface of the first dielectric layer that is farthest from the front side of the substrate;

removing a portion of the insulating layer of the TSV that is farthest from the front side of the substrate to expose a portion of the liner layer of the TSV; and

forming a conductive pad over the TSV, the connection, and at least a portion of the first dielectric layer such that the wire is electrically connected to the TSV by the connection and the conductive pad.

19. The method of claim 18 , wherein the etching of the back side of the substrate includes etching the back side of the substrate to expose the DT capacitor on the back side of the substrate.