Skeleton I/O generation for early ESD analysis
A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.
1. A method comprising:
generating, with a first computing device, data comprising a first physical layout of a plurality input/output (I/O) cells of an integrated circuit in a skeleton form independent from a second physical layout of the plurality of I/O cells that includes functional circuitry of the plurality of I/O cells, wherein the plurality of I/O cells in the skeleton form comprises electrostatic discharge (ESD) protection circuitry and rails but not the functional circuitry of the I/O cells of the integrated circuit;
performing, with a second computing device executing ESD analysis software, an ESD analysis on the data comprising the first physical layout of the plurality of I/O cells in the skeleton form; and
in response to performing the ESD analysis, generating, with the second computing device executing the ESD analysis software, at least one performance characteristic of the ESD circuitry based on the data.
2. The method of claim 1 , wherein the data identifying the first physical layout is formatted according to a Graphic Database System (GDS) format.
3. The method of claim 1 , wherein the at least one performance characteristic comprises a resistance of a discharge path associated with the ESD circuitry.
4. The method of claim 1 , wherein the plurality of I/O cells are part of an I/O pad ring of the integrated circuit.
5. The method of claim 1 , further comprising:
inputting the data to ESD analysis software being executed by the second computing device,
wherein generating the at least one performance characteristics comprises generating, with the second computing device executing the ESD analysis software, the at least one performance characteristic in response to inputting the data to the ESD analysis software.
6. The method of claim 1 , wherein the first computing device and the second computing device are the same computing device.
7. The method of claim 1 , wherein the first computing device and the second computing device are different computing devices.
8. A method comprising:
generating, with a first computing device, a data file for a plurality of input/output (I/O) cells of an integrated circuit independent from a first physical layout of the plurality of I/O cells that includes functional circuitry of the plurality of I/O cells of the integrated circuit, wherein the data file comprises a second physical layout of the plurality of I/O cells that includes information of electrostatic discharge (ESD) circuitry of the plurality of I/O cells and that excludes information of functional circuitry of the plurality of I/O cells;
analyzing, with a second computing device executing electrostatic discharge (ESD) analysis software, the data file comprising the second physical layout of the plurality of I/O cells; and
based on the analysis, generating, with the second computing device executing the ESD analysis software, at least one performance characteristic of ESD circuitry of the integrated circuit.
9. The method of claim 8 , wherein the data file comprises data that identifies ESD protection circuitry and rails of the plurality of I/O cells.
10. The method of claim 8 , wherein the data file comprises a layout data file.
11. The method of claim 8 , wherein the at least one performance characteristic comprises a rail resistance or a path resistance associated with the ESD circuitry.
12. The method of claim 8 , wherein the plurality of I/O cells are part of an I/O pad ring of the integrated circuit.
13. The method of claim 8 , wherein the first computing device and the second computing device are the same computing device.
14. The method of claim 8 , wherein the first computing device and the second computing device are different computing devices.