IP Library Granted Patent US 9,859,180
Granted Patent B2
US 9,859,180 · App. 15/174,450 · Granted Jan 2, 2018

High reliability wafer level semiconductor packaging

Inventor: Yu-Te Hsieh (Taoyuan, TW)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/10H01L21/302H01L23/3114H01L23/481H01L23/49805H01L24/29H01L24/32H01L24/94H01L2224/29021H01L2224/29022H01L2224/29034H01L2224/29099H01L2224/325H01L2224/32013H01L2224/32111H01L2224/32112H01L2224/32237H01L2224/32238H01L2224/83193H01L2224/83856H01L2924/1632H01L2924/1659H01L2924/16788
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Quick Facts
Patent No.
US 9,859,180
App. No.
15/174,450
Granted
Jan 2, 2018
Kind
B2
Abstract

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

Claims (26)

1. A method for making a semiconductor package, the method comprising:

providing a semiconductor wafer and a glass wafer;

forming a trench around a perimeter of one or more semiconductor die of the semiconductor wafer;

forming a trench corresponding with the trench formed around the perimeter of the one or more semiconductor die in the glass wafer;

applying adhesive into the trench of the semiconductor wafer and into the trench in the glass wafer;

coupling the glass wafer to the semiconductor wafer by aligning the trench of the semiconductor wafer with the trench of the glass wafer and using the adhesive in the trenches to bond the semiconductor wafer to the glass wafer, the glass wafer forming one or more corresponding lids for the one or more semiconductor die;

singulating the one or more semiconductor die and the corresponding one or more lids at the trench in the semiconductor wafer to form one or more semiconductor packages;

coupling a redistribution layer to each of the one or more semiconductor packages; and

coupling a plurality of ball mounts to each redistribution layer of the one or more semiconductor packages.

2. The method of claim 1 , wherein the trenches are formed through one of stencil printing, sawing, lasering, wet etching, dry etching and any combination thereof.

3. The method of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

4. The method of claim 1 , wherein the adhesive is applied by one of dispensing, spin coating, lithography, spray coating, stencil printing and any combination thereof.

5. The method of claim 1 , further comprising partially curing the adhesive before coupling the glass wafer to the semiconductor wafer.

6. The method of claim 1 , further comprising coupling the glass wafer and the semiconductor wafer using one of heat compression, ultraviolet light exposure, and any combination thereof.

7. A method for making a semiconductor package, the method comprising:

providing a semiconductor wafer and a glass wafer;

forming a trench around a perimeter of one or more semiconductor die of the semiconductor wafer;

forming a trench corresponding with the trench formed around the perimeter of the one or more semiconductor die in the glass wafer;

applying adhesive into the trench of the semiconductor wafer and into the trench in the glass wafer;

coupling the glass wafer to the semiconductor wafer by aligning the trench of the semiconductor wafer with the trench of the glass wafer and using the adhesive in the trenches to bond the semiconductor wafer to the glass wafer, the glass wafer forming one or more corresponding lids for the one or more semiconductor die; and

singulating the one or more semiconductor die and the corresponding one or more lids at the trench in the semiconductor wafer to form one or more semiconductor packages.

8. The method of claim 7 , wherein the trenches are formed through one of stencil printing, sawing, lasering, wet etching, dry etching and any combination thereof.

9. The method of claim 7 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

10. The method of claim 7 , wherein the adhesive is applied by one of dispensing, spin coating, lithography, spray coating, stencil printing and any combination thereof.

11. The method of claim 7 , further comprising partially curing the adhesive before coupling the glass wafer to the semiconductor wafer.

12. The method of claim 7 , further comprising coupling the glass wafer and the semiconductor wafer using one of heat compression, ultraviolet light exposure, and any combination thereof.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2016
From: HSIEH, YU-TE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038820/0399 →
Continuity (2)
Provisional Application 62296435 · Feb 17, 2016
Related Publication 20170236761A1 · Aug 17, 2017