Tiled-stress-alleviating pad structure

1. A method for fabricating a semiconductor device, the method comprising:

providing a pad layer over a last level of an integrated circuit having a dielectric layer and a metal wiring, wherein the last level is located on a substrate structure and the pad layer directly contacts the dielectric layer and the metal wiring; and

patterning the pad layer to provide a tiled-stress-alleviating pad structure over the metal wiring of the last level, wherein the tiled-stress-alleviating pad structure comprises a plurality of tiles, each tile of the tiled-stress-alleviating pad structure has a set geometry, and is at a set distance from immediately adjacent tiles of the tiled-stress-alleviating pad structure, wherein a first tile of the plurality of tiles overlies the dielectric layer and a second tile of the plurality of tiles overlies the metal wiring.

2. The method of claim 1 , wherein the tiles of the tiled-stress-alleviating pad structure are conductive.

3. The method of claim 2 , wherein each tile of the tiled-stress-alleviating pad structure has an area within a range from about 3,000 nm 2 to about 30,000 nm 2 .

4. The method of claim 1 , wherein the set distance is within a range from about 1,500 nm to about 2,000 nm.

5. The method of claim 1 , wherein the set geometry comprises at least one of a circle and a polygon, and wherein the plurality of tiles is in an array.

6. The method of claim 5 , wherein the set geometry is a hexagonal-shape, and the array forms a honeycomb pattern.

7. The method of claim 5 , wherein the set geometry is a circular-shape, and the array is at least one of a 2×2 and an n×n array.

8. The method of claim 5 , wherein a sum of an area of tiles covering the metal wiring is greater than another sum of another area of tiles covering the dielectric layer of the last level.

9. The method of claim 1 , wherein each tile of the tiled-stress-alleviating pad structure comprises an interior angle that is greater than or equal to about 120°.

10. The method of claim 1 , further comprising a passivating layer via and a ball-limiting metallurgy (BLM) layer disposed over the tiled-stress-alleviating pad structure.

11. The method of claim 10 , wherein the tiled-stress-alleviating pad structure is centered within the passivating layer via.

12. The method of claim 1 , wherein a sum of an area of tiles covering the metal wiring is less than another sum of another area of tiles covering the dielectric layer of the last level.