Integrated circuit structure having through-silicon via and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.
1. A method of forming an integrated circuit structure, the method comprising:
removing a portion of a wafer to expose a through-silicon-via (TSV) on a back side of the wafer;
forming a first passivation layer over the exposed TSV and over the back side of the wafer;
forming a first dielectric layer over the first passivation layer over the back side of the wafer, the first dielectric layer including a first opening that exposes a first portion of the first passivation layer over the TSV and a second portion of the first passivation layer in an area adjacent to the TSV;
forming a first seed layer over the back side of the wafer and within the first opening over the exposed first and second portions of the first passivation layer;
forming a first metal over the back side of the wafer and within the first opening over the first seed layer;
planarizing the first metal, the first passivation layer, and the TSV to a top surface of the first dielectric layer and to expose a second metal of the TSV; and
forming a conductive pad over the first metal and the TSV such that the conductive pad provides electrical connection between the second metal of the TSV and the first metal.
2. The method of claim 1 , wherein the forming of the conductive pad includes:
forming a second dielectric layer over the first metal and the TSV over the back side of the wafer;
patterning and etching the second dielectric layer to create a second opening that exposes the first metal and the second metal of the TSV;
forming a second seed layer within the second opening over the exposed first metal and the exposed second metal of the TSV; and
electroplating a third metal over the second seed layer within the second opening.
3. The method of claim 2 , wherein the second seed layer is a material distinct from the first seed layer.
4. The method of claim 2 , wherein the first seed layer and the second seed layer each include at least one of: titanium, titanium nitride, titanium tungsten, tantalum nitride, copper, tungsten, titanium copper, titanium tungsten copper, tantalum or combinations thereof.
5. The method of claim 2 , wherein the first, second, and third metals each include at least one of: copper, tungsten, tantalum, or titanium.
6. The method of claim 1 , wherein the forming the first passivation layer includes:
forming an oxide layer and a nitride layer over the exposed TSV.
7. The method of claim 1 , further comprising:
forming a second dielectric layer over the conductive pad and over the back side of the wafer;
forming a second opening in the second dielectric layer; and
forming a second seed layer and a third metal within the second opening.
8. The method of claim 1 , wherein a portion of the first dielectric layer is disposed between the first passivation layer and the first seed layer adjacent to the TSV.
9. A method of forming an integrated circuit structure, the method comprising:
removing a portion of a wafer to expose a through-silicon-via (TSV) on a back side of the wafer;
forming a first passivation layer over the exposed TSV and over the back side of the wafer;
forming a first dielectric layer over the first passivation layer over the back side of the wafer, the first dielectric layer including a first opening that exposes a first portion of the first passivation layer over the TSV and a second portion of the first passivation layer in an area adjacent to the TSV;
forming a first seed layer over the back side of the wafer and within the first opening over the exposed first and second portions of the first passivation layer;
forming a first metal over the back side of the wafer and within the first opening over the first seed layer;
planarizing the first metal, the first passivation layer, and the TSV to a top surface of the first dielectric layer and to expose a second metal of the TSV; and
forming a conductive pad over the first metal and the TSV such that the conductive pad provides electrical connection between the second metal of the TSV and the first metal, the conductive pad including a second seed layer and a third metal,
wherein the second seed layer is distinct from the first seed layer.
10. The method of claim 9 , wherein the forming of the conductive pad includes:
forming a second dielectric layer over the first metal and the TSV over the back side of the wafer;
patterning and etching the second dielectric layer to create a second opening that exposes the first metal and the second metal of the TSV;
forming the second seed layer within the second opening over the exposed first metal and the exposed second metal of the TSV; and
electroplating the third metal over the second seed layer within the second opening.
11. The method of claim 9 , further comprising:
forming a second dielectric layer over the conductive pad and over the back side of the wafer;
forming a second opening in the second dielectric layer; and
forming a second seed layer and a third metal within the second opening.
12. The method of claim 9 , wherein the first metal, the second metal, and the third metal each include at least one of: copper, tungsten, tantalum, or titanium.
13. The method of claim 9 , wherein the forming the first passivation layer includes:
forming an oxide layer and a nitride layer over the exposed TSV.
14. An integrated circuit structure having a front side and back side opposing the front side, the integrated circuit structure comprising:
a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side;
a first metal adjacent to the TSV and within a first seed layer within the dielectric layer;
a second metal adjacent to the TSV on an opposing side of the TSV relative to the first metal, the second metal being within a second seed layer within the dielectric layer; and
a conductive pad over the first metal, the second metal, and the TSV, and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV, the second metal, and the first metal, and wherein the conductive pad includes a third metal within a third seed layer,
wherein the third seed layer separates the third metal from the first metal the second metal, and the TSV.
15. The integrated circuit structure of claim 14 , wherein the first seed layer and second seed layer are distinct from the third seed layer.
16. The integrated circuit structure of claim 14 , wherein the first metal, the second metal, and the third metal each comprise at least one of: copper, tungsten, tantalum, or titanium.
17. The integrated circuit structure 14 , further comprising:
a nitride passivation layer and an oxide passivation layer substantially surrounding the TSV such that the nitride passivation layer and the oxide layer are disposed between the TSV and the first seed layer.
18. The integrated circuit structure of claim 14 , wherein a portion of the dielectric layer is disposed between the TSV and the first metal.
19. The integrated circuit structure of claim 14 , wherein the TSV is approximately 5 microns thick.
20. The integrated circuit structure of claim 14 , wherein the first metal and second metal each include a sloped sidewall.