IP Library › Granted Patent US 9,929,253
Granted Patent B2
US 9,929,253 · App. 15/178,853 · Granted Mar 27, 2018

Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth

Inventors: Xiuyu Cai (Niskayuna, NY); Qing Liu (Watervliet, NY); Ruilong Xie (Niskayuna, NY); Chun-Chen Yeh (Clifton Park, NY)
Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION; STMICROELECTRONICS, INC.; GLOBALFOUNDRIES INC.
H01L29/66795H01L21/0228H01L21/02164H01L21/02178H01L21/31105H01L21/823814H01L21/823821H01L27/0924H01L29/0847H01L29/1033H01L29/785H01L29/7851H01L29/165
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,929,253
App. No.
15/178,853
Granted
Mar 27, 2018
Kind
B2
Abstract

A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Claims (28)

1. A method for making a semiconductor device comprising:

forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins;

forming at least one dielectric layer, the at least one dielectric layer covering the plurality of semiconductor fins and the substrate between adjacent semiconductor fins;

forming a pair of sidewall spacers adjacent outermost semiconductor fins at the end portion of the plurality of semiconductor fins;

removing the at least one dielectric layer and end portion of the plurality of semiconductor fins between the pair of sidewall spacers; and

forming source/drain regions between the pair of sidewall spacers.

2. The method according to claim 1 forming source/drain regions comprises epitaxially growing the source/drain regions.

3. The method according to claim 2 wherein the source/drain regions comprise silicon.

4. The method according to claim 2 wherein the source/drain regions comprise silicon germanium.

5. The method according to claim 1 wherein forming the at least one dielectric layer comprises:

forming a first dielectric layer comprising a first dielectric material on the end portion of the plurality of semiconductor fins; and

forming a second dielectric layer comprising a second dielectric material different than the first dielectric material on the first dielectric layer and with the second dielectric material filling the space between adjacent semiconductor fins.

6. The method according to claim 5 further comprising, before forming the sidewall spacers, removing portions of the second dielectric layer laterally adjacent the outermost semiconductor fins and above the semiconductor fins while retaining portions of the second dielectric layer filling the space between adjacent semiconductor fins.

7. The method according to claim 5 wherein forming the second dielectric layer comprises atomic layer deposition thereof.

8. The method according to claim 1 further comprising forming a gate overlying the plurality of semiconductor fins.

9. The method according to claim 1 wherein the semiconductor fins comprise silicon.

10. The method according to claim 1 wherein the substrate comprises a semiconductor substrate.

11. A method for making a semiconductor device comprising:

forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins;

forming a first dielectric layer comprising a first dielectric material adjacent an end portion of the plurality of semiconductor fins;

forming a second dielectric layer comprising a second dielectric material different than the first dielectric material on the first dielectric layer and with the second dielectric material filling the space between adjacent semiconductor fins;

forming a pair of sidewall spacers adjacent outermost semiconductor fins at the end portion of the plurality of semiconductor fins;

removing at least portions of the second dielectric layer and the end portion of the plurality of semiconductor fins between the pair of sidewall spacers; and

epitaxially forming source/drain regions between the pair of sidewall spacers.

12. The method according to claim 11 further comprising, before forming the sidewall spacers, removing portions of the second dielectric layer laterally adjacent the outermost semiconductor fins and above the semiconductor fins while retaining portions of the second dielectric layer filling the space between adjacent semiconductor fins.

13. The method according to claim 11 wherein forming the second dielectric layer comprises atomic layer deposition thereof.

14. The method according to claim 11 further comprising forming a gate overlying the plurality of semiconductor fins.

15. The method according to claim 11 wherein the semiconductor fins and the substrate each comprises silicon.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054479/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2020
From: GLOBALFOUNDRIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054482/0862 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2016
From: YEH, CHUN-CHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038877/0282 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2016
From: CAI, XIUYU; XIE, RUILONG
To: GLOBALFOUNDRIES INC.
Reel/Frame 038877/0858 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2016
From: LIU, QING
To: STMICROELECTRONICS, INC.
Reel/Frame 038878/0089 →
Continuity (2)
Division 14288766 · May 28, 2014
Related Publication 20160284822A1 · Sep 29, 2016