Semiconductor package
A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.
1. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads comprising a power lead disposed along a peripheral edge of the die pad;
at least one connecting bar connecting with the die pad via a ground bar;
a power bar disposed on one side of the connecting bar, wherein the power bar is integrally connected to the power lead and extends along peripheral edges of the die pad; and
a capacitor electrically coupled between the power bar and the connecting bar.
2. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads comprising a power lead disposed along a peripheral edge of the die pad;
at least one connecting bar connecting the die pad;
a power bar disposed on one side of the connecting bar, wherein the power bar is integrally connected to the power lead and is flush with the die pad; and
a capacitor mounted between the power bar and the die pad.
3. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads comprising a power lead disposed along a peripheral edge of the die pad;
at least one connecting bar connecting the die pad;
a ground bar disposed on one side of the connecting bar, wherein the ground bar is integrally connected to the die pad;
a power bar disposed on one side of the connecting bar, wherein the power bar is integrally connected to the power lead and is flush with the around bar; and
a capacitor mounted between the power bar and the ground bar.
4. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads comprising a power lead disposed along a peripheral edge of the die pad;
at least one connecting bar connecting the die pad; and
a surface mount device (SMD) comprising a first terminal and a second terminal, wherein the first terminal is electrically connected to a ground level through a first bond wire, and wherein the second terminal is electrically connected a power level through a second bond wire.
5. The semiconductor package according to claim 4 , wherein a bottom surface of the die pad is exposed outside the semiconductor package.
6. The semiconductor package according to claim 4 further comprising a molding compound at least partially encapsulating the die pad, and the leads.
7. The semiconductor package according to claim 4 , wherein the SMD is mounted in the semiconductor package by using a non-conductive paste.
8. The semiconductor package according to claim 4 , wherein the SMD overlaps with and electrically isolated from the leads.
9. The semiconductor package according to claim 4 , wherein the first terminal is electrically connected to a ground pad on the semiconductor die, a ground bar, the die pad, the connecting bar, or a ground lead of the leads.
10. The semiconductor package according to claim 4 , wherein the second terminal is electrically connected to power pads on the semiconductor die, a power bar, or the power lead of the leads.
11. The semiconductor package according to claim 4 , wherein the SMD is mounted on an active top surface of the semiconductor die.
12. The semiconductor package according to claim 4 , wherein the SMD is mounted on the die pad.
13. The semiconductor package according to claim 4 , wherein the SMD is mounted on a substrate.
14. The semiconductor package according to claim 13 , wherein the substrate comprises single-layer or multi-layer traces, wiring, via-plug or circuit patterns.
15. The semiconductor package according to claim 4 , wherein the SMD comprises a passive discrete device.
16. The semiconductor package according to claim 15 , wherein the passive discrete device comprises a resistor, an inductor, a capacitor, an RLC (resistor-inductor-capacitor) device, an ESD (electrostatic discharge) device, an IPD (integrated passive device), or a crystal oscillator device.
17. The semiconductor package according to claim 4 , wherein the first terminal and the second terminal of the SMD are plated with noble metal comprising gold (Au), silver (Ag), platinum (Pt), or palladium (Pd).