Method of forming complementary metal oxide semiconductor device with work function layer
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
1. A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:
providing a dielectric layer, having a first trench and a second trench;
forming a bottom barrier layer and a P work function metal (PWFM) layer in the first trench and the second trench;
removing the bottom barrier layer and the PWFM layer in the second trench;
forming an N work function tuning (NWFT) layer and a N work function metal (NWFM) layer in the first trench and the second trench, wherein the NWFT layer is disposed between the PWFM layer and the NWFM layer in the first trench and directly contacts the PWFM layer and the NWFM layer; and
forming a metal layer to completely fill the first trench and the second trench.
2. The method of forming a CMOS device according to claim 1 , wherein before forming the bottom barrier layer, further comprises forming an etch stop layer in the second trench.
3. The method of forming a CMOS device according to claim 2 , wherein in the step of removing the bottom barrier layer and the PWFM layer in the second trench, the etch stop layer is used as a stop layer.
4. The method of forming a CMOS device according to claim 1 , wherein the NWFT layer comprises TiN or TaN.
5. The method of forming a CMOS device according to claim 4 , wherein the step of forming the NWFT layer comprises a nitrogen treatment process.
6. The method of forming a CMOS device according to claim 5 , wherein in the nitrogen treatment process, the first trench is covered by a mask.
7. The method of forming a CMOS device according to claim 1 , wherein before forming the metal layer, further comprises forming a top barrier layer on the NWFM layer.
8. The method of forming a CMOS device according to claim 7 , wherein the bottom barrier layer comprises a first bottom barrier layer and a second bottom barrier layer.
9. The method of forming a CMOS device according to claim 8 , wherein the first bottom barrier layer comprises TiN and the second bottom barrier layer comprises TiN.
10. The method of forming a CMOS device according to claim 7 , wherein the NWFM layer is disposed between the NWFT layer and the top barrier layer and has a different material from materials of the NWFT layer and the top barrier layer.