Interface compatible with M.2 connector socket for ultra high capacity solid state drive
A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.
1. A solid state drive, comprising:
a controller board, comprising a plurality of card-edge connector sockets; and
a plurality of memory cards on the controller board,
a first memory card of the plurality of memory cards comprising:
a memory package comprising a flash memory die; and
a first card-edge connector plug,
the first card-edge connector plug being coupled to a first connector socket of the plurality of card-edge connector sockets,
wherein the first connector socket is an M.2 connector socket having a plurality of pins, and
wherein the controller board is configured to provide and/or receive, at a plurality of first bus pins of the pins of the M.2 connector socket, a plurality of signals compliant with an Open NAND Flash Interface (ONFI) standard or with a Toggle standard.
2. The solid state drive of claim 1 , wherein the signals include:
an address latch enable signal;
a command latch enable signal;
a differential pair of read enable signals;
a write enable signal;
a differential pair of data strobe signals; and
eight input-output port bit signals.
3. The solid state drive of claim 2 , wherein:
the controller board is configured to provide and/or receive the differential pair of read enable signals on a pair of adjacent pins of the M.2 connector socket, and
the controller board is configured to provide and/or receive the signals of the differential pair of data strobe signals on a pair of adjacent pins of the M.2 connector socket.
4. The solid state drive of claim 3 , wherein the controller board further comprises a solid state drive controller, the solid state drive controller being a processing circuit and having a first flash channel interface, and configured to provide and/or receive, at a plurality of first flash channel pins of the solid state drive controller, a plurality of signals compliant with an Open NAND Flash Interface (ONFI) standard or with a Toggle standard.
5. The solid state drive of claim 4 , wherein the controller board further comprises an analog switch configured to selectively connect the first flash channel pins:
to the first bus pins of the M.2 connector socket, or
to a plurality of second bus pins of the pins of the M.2 connector socket.
6. A solid state drive, comprising:
a controller board, comprising a plurality of card-edge connector sockets; and
a plurality of memory cards on the controller board,
a first memory card of the plurality of memory cards comprising:
a memory package comprising a flash memory die; and
a first card-edge connector plug,
the first card-edge connector plug being coupled to a first connector socket of the plurality of card-edge connector sockets,
wherein the first connector socket is an M.2 connector socket having a plurality of pins, and
wherein the solid state drive further comprises a solid state drive controller on the controller board, the solid state drive controller being configured to communicate with the first memory card only through the M.2 connector socket and to provide and/or receive, at a plurality of first bus pins of the pins of the M.2 connector socket, a plurality of signals compliant with an Open NAND Flash Interface (ONFI) standard or with a Toggle standard, wherein the signals include:
an address latch enable signal;
a command latch enable signal;
a differential pair of read enable signals;
a write enable signal;
a differential pair of data strobe signals; and
eight input-output port bit signals.