IP Library › Granted Patent US 10,147,603
Granted Patent B2
US 10,147,603 · App. 15/197,004 · Granted Dec 4, 2018

Method of manufacturing a FET using a two dimensional transition metal dichalcogenide including a low power oxygen plasma treatment

Inventors: Shih-Yen Lin (Hsinchu, TW); Chi-Wen Liu (Hsinchu, TW); Si-Chen Lee (Taipei, TW); Chong-Rong Wu (New Taipei, TW); Kuan-Chao Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/02568H01L21/02694H01L21/324H01L29/66742
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Quick Facts
Patent No.
US 10,147,603
App. No.
15/197,004
Granted
Dec 4, 2018
Kind
B2
Abstract

In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS 2 layer. Source and drain electrodes are formed on the MoS 2 layer. The MoS 2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS 2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

Claims (38)

1. A method of fabricating a field effect transistor, comprising:

forming a transition metal dichalcogenide (TMD) layer on a substrate; and

treating the TMD layer with low-power oxygen plasma to reduce defects in the TMD layer by forming metal-oxygen bonds, wherein the low-powered oxygen plasma treating causes an increase in electron concentrations in the TMD layer and an increased field-effect mobility values in the TMD layer,

wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 35 W.

2. The method of claim 1 , wherein the TMD layer includes at least one of MoS 2 and WS 2 .

3. The method of claim 1 , wherein the TMD layer includes MoS 2 .

4. The method of claim 3 , wherein the forming the MoS 2 layer includes:

forming a Mo layer on the substrate; and

sulfurizing the Mo layer, thereby converting the Mo layer into the MoS 2 layer.

5. The method of claim 4 , wherein in the sulfurizing the Mo layer, the substrate is heated at a temperature in a range from 700° C. to 900° C.

6. The method of claim 3 , wherein the input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

7. The method of claim 3 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

8. The method of claim 3 , wherein the low-power oxygen plasma treatment is performed for 3 sec to 10 sec.

9. The method of claim 6 , wherein in the low-power oxygen plasma treatment, a DC bias in a range from 20 V to 40 V is applied to the substrate.

10. A method of fabricating a field effect transistor, comprising:

forming a MoS 2 layer on a first substrate;

forming a gate dielectric layer on a second conductive substrate;

forming source and drain electrodes on the gate dielectric layer;

detaching the MoS 2 layer from the first substrate and attaching the detached MoS 2 layer on the gate dielectric layer and the source and drain electrodes; and

treating the MoS 2 layer with low-power oxygen plasma,

wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

11. The method of claim 10 , wherein an input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

12. The method of claim 10 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

13. The method of claim 10 , wherein the low-power oxygen plasma treatment is performed for 3 sec to 10 sec.

14. The method of claim 10 , wherein in the low-power oxygen plasma treatment, a DC bias in a range from 20 V to 40 V is applied to the substrate.

15. The method of claim 10 , wherein the source and drain electrodes include at least one of Au, Ag and Ti.

16. A method of fabricating a field effect transistor, comprising:

forming a Mo layer on a substrate;

sulfurizing the Mo layer into a MoS 2 layer;

forming source and drain electrodes on the MoS 2 layer;

treating the MoS 2 layer with low-power oxygen plasma;

forming a gate dielectric layer on the MoS 2 layer; and

forming a gate electrode on the gate dielectric layer,

wherein an input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.

17. The method of claim 16 , wherein an input electric power in the low-power oxygen plasma treatment is in a range from 20 W to 35 W.

18. The method of claim 16 , the low-power oxygen plasma treatment is performed after the source and drain electrodes are formed and before the gate dielectric layer is formed.

19. The method of claim 16 , wherein the low-power oxygen plasma treatment is performed for 1 sec to 20 sec.

20. The method of claim 16 , wherein in the sulfurizing the Mo layer, the substrate is heated at a temperature in a range from 700° C. to 900° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2016
From: LIN, SHIH-YEN; LIU, CHI-WEN; LEE, SI-CHEN; WU, CHONG-RONG; CHEN, KUAN-CHAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.; NATIONAL TAIWAN UNIVERSITY
Reel/Frame 039435/0887 →
Continuity (1)
Related Publication 20180005824A1 · Jan 4, 2018
Cited By (1)
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