Semiconductor structure and manufacturing method thereof
The present disclosure in various embodiments provides a method. In some embodiments of the present disclosure, the method includes forming a transition metal dichalcogenide layer on a substrate; and performing an ion bombardment process on the transition metal dichalcogenide layer, performing an annealing process on the transition metal dichalcogenide layer.
1 . A method, comprising:
forming a transition metal dichalcogenide (TMD) layer on a first substrate;
forming a source/drain contact over the TMD layer;
after forming the source/drain contact, performing an ion bombardment process through the source/drain contact to the underlying TMD layer; and
performing an annealing process on the TMD layer.
2 . The method of claim 1 , wherein the annealing process is performed after the ion bombardment process.
3 . The method of claim 1 , wherein the ion bombardment process and the annealing process are performed simultaneously.
4 . The method of claim 1 , further comprising:
after performing the ion bombardment process and the annealing process, transferring the TMD layer from the first substrate onto a second substrate.
5 . The method of claim 1 , further comprising:
before performing the ion bombardment process and the annealing process, transferring the TMD layer from the first substrate onto a second substrate.
6 . The method of claim 1 , further comprising:
introducing a chalcogen-containing precursor on the TMD layer during the annealing process.
7 . The method of claim 1 , wherein the ion bombardment process is performed by using an inert gas as a bombardment source.
8 . The method of claim 1 , wherein the ion bombardment process has an ion bombardment energy in a range from about 0.1 keV to about 2.0 keV.
9 . The method of claim 1 , wherein the annealing process is performed at a temperature lower than about 600° C.
10 . The method of claim 1 , wherein the annealing process is performed under a pressure lower than about 1×10 −5 Torr.
11 . A method, comprising:
forming a TMD on a substrate;
forming a source/drain contact over the TMD;
after forming the source/drain contact, bombarding the TMD using Ar plasma;
after bombarding the TMD, annealing the TMD; and
introducing a precursor on the TMD, the precursor having a same chalcogen element as the TMD.
12 . The method of claim 11 , wherein the TMD is made of platinum ditelluride, palladium ditelluride, or combinations thereof.
13 . The method of claim 11 , wherein the chalcogen element comprises tellurium, selenium, sulfur, or combinations thereof.
14 . The method of claim 11 , wherein the substrate is made of graphene.
15 . The method of claim 11 , wherein bombarding the TMD is performed in a time duration in a range from about 1 minutes to about 5 minutes.
16 . A method, comprising:
forming a TMD layer on a substrate;
transferring the TMD layer from the substrate onto a wafer, the wafer having a transistor and an interconnect structure over the transistor;
patterning the TMD layer to form a channel region and source/drain regions on opposite sides of the channel region;
after patterning the TMD layer, forming a metal layer, as a mask, over the source/drain regions of the TMD layer while exposing the channel region of the TMD layer;
performing a first ion bombardment process on the exposed channel region of the TMD layer while the source/drain regions remain covered by the metal layer;
after performing the first ion bombardment process, performing a first annealing process on the TMD layer; and
patterning the TMD layer to form a device element.
17 . The method of claim 16 , wherein the TMD layer has a transition metal element comprising platinum, palladium, or combinations thereof.
18 . The method of claim 16 , wherein the first annealing process is performed at a temperature in a range from about 100° C. to about 600° C.
19 . The method of claim 16 , further comprising:
performing a second ion bombardment process on the TMD layer.
20 . The method of claim 19 , further comprising:
after performing the second ion bombardment process, performing a second annealing process on the TMD layer.