Vertical transistors and methods of forming same

1. A vertical transistor comprising:

a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within an inter-level dielectric (ILD) layer and over the central region of the fin; and

a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source/drain region,

wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

2. The vertical transistor of claim 1 , wherein the at least one tapered region includes a first tapered region to the first source/drain region and a second tapered region to the second source/drain region.

3. The vertical transistor of claim 1 , further comprising:

a first epitaxial layer over the substrate within the ILD layer and substantially surrounding the first source/drain region; and

a second epitaxial layer over the ILD layer and over the second source/drain region.

4. The vertical transistor of claim 3 , further comprising a dielectric layer positioned between the first epitaxial layer and the gate structure.

5. The vertical transistor of claim 3 , further comprising a nitride layer positioned between the gate structure and the second epitaxial layer.

6. The vertical transistor of claim 2 , further comprising a gate spacer substantially surrounding the gate structure.

7. The vertical transistor of claim 2 , further comprising, within an area between the first epitaxial layer and the gate structure:

a dielectric layer over the first epitaxial layer;

a nitride layer over the dielectric layer; and

a second dielectric layer over the nitride layer.