Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal cathode lines
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.
1. A plurality of volatile memory cells comprising:
a first silicon thyristor comprising a first cathode formed from a first material;
a second silicon thyristor comprising a second cathode formed from the first material;
a first cathode line, formed from a conductor material, connecting the first cathode of the first silicon thyristor and the second cathode of the second silicon thyristor, and wherein a minority carrier lifetime of a minority carrier is shorter in the conductor material than in the first material; and
a first isolation insulator region separating a first portion of the first silicon thyristor and a second portion of the second silicon thyristor.
2. The plurality of volatile memory cells of claim 1 , wherein the conductor material comprises a metal silicide material formed from a transition metal comprising at least one of a Group 9 metal and a Group 10 metal.
3. The plurality of volatile memory cells of claim 2 , wherein the metal silicide material is formed from the transition metal comprising at least one of cobalt, platinum, palladium, and nickel.
4. The plurality of volatile memory cells of claim 2 , wherein the metal silicide material is formed from the transition metal having a higher diffusivity than silicon during a silicidation reaction at a temperature less than 900 degrees Celsius.
5. The plurality of volatile memory cells of claim 1 , wherein the first cathode line comprises a first metal silicide region merged with a second metal silicide region.
6. The plurality of volatile memory cells of claim 1 , wherein the first silicon thyristor comprises a first anode and the second silicon thyristor comprises a second anode, and wherein the first anode and the second anode are single crystalline silicon regions formed by a selective epitaxial growth process.
7. A memory device comprising:
an array of memory cells, comprising:
a first silicon thyristor comprising a first cathode formed from a first material;
a second silicon thyristor comprising a second cathode formed from the first material;
a third silicon thyristor;
a first cathode line, formed from a conductor material, connecting the first cathode of the first silicon thyristor and the second cathode of the second silicon thyristor, and wherein a minority carrier lifetime of a minority carrier is shorter in the conductor material than in the first material;
a first isolation insulator region separating a first portion of the first silicon thyristor and a second portion of the second silicon thyristor; and
a second isolation insulator region separating a third portion of the first silicon thyristor and a fourth portion of the third silicon thyristor.
8. The memory device of claim 7 , wherein the conductor material comprises a metal silicide material formed from the transition metal having a higher diffusivity than silicon during a silicidation reaction at a temperature less than 900 degrees Celsius.
9. The memory device of claim 7 wherein the first cathode line comprises a first metal silicide region merged with a second metal silicide region.