IP Library Granted Patent US 9,773,682
Granted Patent B1
US 9,773,682 · App. 15/201,628 · Granted Sep 26, 2017

Method of planarizing substrate surface

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Quick Facts
Patent No.
US 9,773,682
App. No.
15/201,628
Granted
Sep 26, 2017
Kind
B1
Abstract

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

Claims (15)

1. A method of planarizing a substrate surface, comprising:

providing a substrate having a major surface of a material layer, wherein the major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate;

forming a photoresist pattern on the major surface of the material layer, wherein the photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate;

etching away at least a portion of the material layer not covered by the photoresist pattern;

removing the photoresist pattern;

depositing a polish stop layer on the major surface of the material layer;

depositing a cap layer on the polish stop layer; and

performing a chemical mechanical polishing (CMP) process to polish the cap layer.

2. The method according to claim 1 , wherein the material layer comprises amorphous silicon.

3. The method according to claim 1 , wherein the CMP process stops on the polish stop layer.

4. The method according to claim 1 , wherein the polish stop layer comprises silicon nitride.

5. The method according to claim 4 , wherein the cap layer comprises silicon oxide or amorphous silicon.

6. The method according to claim 1 , wherein after performing the CMP process to polish the cap layer, the method further comprises:

performing a dry etching process to etch the cap layer, the polishing stop layer, and the material layer.

7. The method according to claim 6 , wherein the dry etching process is performed at substantially same etching rate with respect to the cap layer, the polishing stop layer, and the material layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2016
From: HSU, LI-CHIEH; TSAI, FU-SHOU; LI, YU-TING; LIU, YI-LIANG; LI, KUN-JU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039071/0046 →