Semiconductor device having interconnection structure
View Patent ↗A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.
1. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor pattern on the semiconductor substrate;
a three-dimensional memory array on the semiconductor pattern; and
a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate,
the peripheral interconnection structure including an upper interconnection structure and a lower interconnection structure,
the lower interconnection structure being under the upper interconnection structure,
the upper interconnection structure including an upper interconnection and an upper barrier layer,
the lower interconnection structure including a lower interconnection and a lower barrier layer,
the upper barrier layer being under a bottom surface of the upper interconnection, the upper barrier layer does not cover side surfaces of the upper interconnection,
the lower barrier layer is under a bottom surface of the lower interconnection,
the lower barrier layer covers side surfaces of the lower interconnection.
2. The device of claim 1 , wherein a thickness of the upper interconnection is greater than a thickness of the lower interconnection.
3. The device of claim 1 , wherein
the side surfaces of the upper interconnection have positive slopes, and
the side surfaces of the lower interconnection have negative slopes.
4. The device of claim 1 , wherein the lower interconnection structure further includes a lower contact plug under the lower interconnection.
5. The device of claim 4 , wherein the lower contact plug is integrally formed with the lower interconnection.
6. The device of claim 4 , wherein the lower barrier layer extends on side surfaces and a bottom surface of the lower contact plug.
7. The device of claim 4 , wherein
the lower interconnection structure further includes a lower conductive layer,
the lower conductive layer is on the bottom surface and the side surfaces of the lower interconnection,
the lower conductive layer extends on side surfaces of the lower contact plug,
the lower barrier layer is between the lower conductive layer and the lower interconnection, and
the lower barrier layer extends between the lower conductive layer and the lower contact plug.
8. The device of claim 1 , wherein
the upper interconnection structure further includes an upper contact plug between the upper interconnection and the lower interconnection.
9. The device of claim 8 , wherein
the upper contact plug is integrally formed with the upper interconnection, and
the upper barrier layer extends so as to cover side surfaces and a lower surface of the upper contact plug.
10. The device of claim 1 , wherein
the three-dimensional memory array includes a plurality memory cells, and
each of the memory cells includes a charge trap layer.
11. The device of claim 1 , wherein
the three-dimensional memory array includes a plurality of memory strings, and
the memory strings are perpendicular to the semiconductor pattern.