Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed.
1. A semiconductor device comprising:
a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and
a semiconductor die comprising a first contact pad electrically coupled to the conductive substrate, wherein the first contact pad is soldered to both the first planar surface of the first elevated region and the second planar surface of the second elevated region, and wherein only a portion of the first planar surface is soldered to the first contact pad.
2. The semiconductor device of claim 1 , wherein the conductive substrate comprises at least 10 elevated regions.
3. The semiconductor device of claim 1 , wherein the conductive substrate and the semiconductor die are at least partially encapsulated in a molding material.
4. The semiconductor device of claim 3 , wherein the molding material is disposed between the first elevated region and the second elevated region.
5. The semiconductor device of claim 1 , wherein the second planar surface of the second elevated region has a first corner that is laterally aligned with a first corner of the first contact pad.
6. The semiconductor device of claim 1 , wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate, wherein the third elevated comprises a third planar surface on the first side of the conductive substrate, and wherein the first contact pad is soldered to the third planar surface of the third elevated region.
7. The semiconductor device of claim 6 , wherein only a potion of the third planar surface is soldered to the first contact pad.
8. The semiconductor device of claim 1 , wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region.
9. The semiconductor device of claim 1 , wherein the conductive substrate further comprises a third elevated region on a first side of the conductive substrate, wherein the third elevated region comprises a third planar surface on the first side of the conductive substrate, and wherein the semiconductor die further comprises a second contact pad electrically coupled to the conductive substrate, wherein the second contact pad is soldered to the third planar surface.
10. The semiconductor device of claim 1 , wherein the semiconductor die is a metal-oxide field-effect transistor (MOSFET).
11. A semiconductor device comprising:
a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate, and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and
a semiconductor die comprising a first contact pad electrically coupled to the conductive substrate, wherein the first contact pad is soldered to the first planar surface of the first elevated region, wherein the second planar surface of the second elevated region is not soldered to the semiconductor die, and wherein the second planar surface of the second elevated region is laterally positioned away from a footprint of the semiconductor die.
12. The semiconductor device of claim 11 , wherein the conductive substrate and the semiconductor die are at least partially encapsulated in a molding material.
13. The semiconductor device of claim 12 , wherein the molding material is disposed between the first elevated region and the second elevated region.
14. The semiconductor device of claim 11 , wherein the first planar surface of the first elevated region has a first corner that is laterally aligned with a first corner of the first contact pad.
15. The semiconductor device of claim 11 , wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region.
16. The semiconductor device of claim 11 , wherein the conductive substrate comprises at least 10 elevated regions.
17. The semiconductor device of claim 11 , wherein the conductive substrate further comprises a third elevated region on a first side of the conductive substrate, wherein the third elevated region comprises a third planar surface on the first side of the conductive substrate, and wherein the semiconductor die further comprises a second contact pad electrically coupled to the conductive substrate, wherein the second contact pad is soldered to the third planar surface.
18. The semiconductor device of claim 11 , wherein the semiconductor die is a metal-oxide field-effect transistor (MOSFET).
19. The semiconductor device of claim 11 , wherein the conductive substrate further comprises a third elevated region on a first side of the conductive substrate, wherein the third elevated region comprises a third planar surface on the first side of the conductive substrate, and wherein the third planar surface of the third elevated region is not soldered to the semiconductor die, and wherein the third planar surface of the third elevated region is laterally positioned away from a footprint of the semiconductor die.
20. The semiconductor die of claim 19 , wherein the third planar surface has the same dimensions as the second planar surface.