IP Library Granted Patent US 9,735,288
Granted Patent B2
US 9,735,288 · App. 15/204,394 · Granted Aug 15, 2017

One time programmable non-volatile memory device

Inventors: Tae Ho Kim (Cheongju-si, KR); Kyung Ho Lee (Cheongju-si, KR); Young Chul Seo (Gwangmyeong-si, KR); Sung Jin Choi (Cheongju-si, KR)
Assignee: Magnachip Semiconductor, Ltd.
H01L29/7885H01L29/42328H01L29/66825H01L29/7833
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Quick Facts
Patent No.
US 9,735,288
App. No.
15/204,394
Granted
Aug 15, 2017
Kind
B2
Abstract

A one-time programmable non-volatile memory device includes a first conductivity type well region located in a semiconductor substrate, a selection gate electrode and a floating gate electrode located on the substrate, a first doped region located between the selection gate electrode and the floating gate electrode, a second conductivity type source region located on one side of the selection gate electrode, and a second conductivity type drain region located on one side of the floating gate electrode, wherein a depth of the drain region has a depth shallower than that of the first doped region with respect to a top surface of the substrate.

Claims (32)

1. A one-time programmable non-volatile memory device, comprising:

a first conductivity type well region located in a semiconductor substrate;

a selection gate electrode and a floating gate electrode located on the substrate;

a first doped region located between the selection gate electrode and the floating gate electrode, the first doped region overlapping with the floating gate electrode and the selection gate electrode;

a second conductivity type source region located on one side of the selection gate electrode; and

a second conductivity type drain region located on one side of the floating gate electrode, wherein

a depth of the drain region has a shallower depth than that of the first doped region with respect to a top surface of the substrate.

2. The one-time programmable non-volatile memory device of claim 1 , further comprising a contact plug located on the source and drain regions, and wherein the contact plug is not located on the first doped region.

3. The one-time programmable non-volatile memory device of claim 1 , wherein the first doped region comprises a heavily doped region and a lightly doped region, and the drain region comprises a lightly doped region that is blocked.

4. The one-time programmable non-volatile memory device of claim 1 , further comprising a third doped region located between the drain region and the well region, wherein the third doped region completely surrounds the drain region, and has an opposite conductivity type from the drain region.

5. The one-time programmable non-volatile memory device of claim 1 , further comprising a third doped region located between the drain region and the well region, wherein the third doped region has a shallower depth than that of the first doped region, and has a same conductivity type as the drain region.

6. The one-time programmable non-volatile memory device of claim 1 , further comprising a third doped region formed between the drain region and the well region, wherein the third doped region completely surrounds the drain region, and has a lower dopant concentration than the drain region.

7. The one-time programmable non-volatile memory device of claim 1 , further comprising a contact plug located on the selection gate electrode, wherein the contact plug is not located on the floating gate electrode, and the selection gate electrode and the floating gate electrode are doped with a dopant of the second conductivity type.

8. The one-time programmable non-volatile memory device of claim 7 , wherein the contact plug is a word line contact plug, a bit line contact plug, or a source line contact plug.

9. The one-time programmable non-volatile memory device of claim 1 , wherein the source region comprises a heavily doped region and a lightly doped region, and a depth of the source region is deeper than a depth of the drain region.

10. The one-time programmable non-volatile memory device of claim 1 , further comprising a silicide layer located on the selection gate electrode, wherein a silicide blocking layer is located on the floating gate electrode.

11. The one-time programmable non-volatile memory device of claim 10 , wherein the silicide blocking layer is a silicon oxide layer or a silicon nitride layer.

12. A one-time programmable non-volatile memory device comprising:

a semiconductor substrate comprising an active region and an isolation region;

at least one pair of floating gate regions located on the substrate;

at least one pair of selection gate electrodes located on the external side of the at least one pair of floating gate electrodes;

a drain region located between the floating gate electrodes;

a first doped region located between the selection gate electrode and the floating gate electrode;

a source region located on one side of the selection gate electrode; and

a well region located to surround the source region and the drain region, wherein

the drain region has a shallower depth than that of the first doped region with respect to a top surface of the substrate.

13. The one-time programmable non-volatile memory device of claim 12 , wherein the first doped region comprises a heavily doped region and a lightly doped region and the lightly doped region is blocked in the drain region.

14. The one-time programmable non-volatile memory device of claim 12 , wherein a length of the floating gate electrode is shorter than a length of the selection gate electrode.

15. The one-time programmable non-volatile memory device of claim 12 , further comprising a contact plug located on the source region and the drain region and wherein the contact plug is not located on the first doped region.

16. The one-time programmable non-volatile memory device of claim 12 , further comprising a contact plug located on the selection gate electrode, wherein the contact plug is not located on the floating gate electrode, and the selection gate electrode and the floating gate electrode are doped with a dopant of a second conductivity type.

17. The one-time programmable non-volatile memory device of claim 12 , wherein the source region comprises a heavily doped source region and a lightly doped source region and a depth of the source region is deeper than a depth of the drain region.

18. The one-time programmable non-volatile memory device of claim 12 , further comprising a silicide layer located on the selection gate electrode, wherein the silicide layer is not located on the floating gate electrode.

Assignments (3)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2016
From: KIM, TAE HO; LEE, KYUNG HO; SEO, YOUNG CHUL; CHOI, SUNG JIN
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 039102/0437 →
Priority Claims (1)
KR 10-2015-0182227 · Dec 18, 2015 · national
Continuity (1)
Related Publication 20170179297A1 · Jun 22, 2017