Electronic component package having stress alleviation structure
An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.
1. A semiconductor package comprising:
a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer;
a semiconductor chip disposed on the wiring part;
a frame disposed on the wiring part, having upper and lower surfaces opposing each other, and including a component disposition region defined by an inner wall of the frame surrounding the semiconductor chip; and
an encapsulant filling at least a portion of the component disposition region,
wherein a portion of the inner wall of the frame has first and second protrusions, made of an insulating material and disposed on opposite sides of the semiconductor chip, protruding toward the semiconductor chip,
each of the first and second protrusions has an upper surface, a lower surface opposing the upper surface, and an end surface connecting the upper and lower surfaces of a respective one of the first and second protrusions and opposing the inner wall of the frame, the semiconductor chip disposed between the end surfaces of the first and second protrusions,
the upper surface of the frame and the upper surface of each of the first and second protrusions have a first step, and the lower surface of the frame and the lower surface of each of the first and second protrusions have a second step,
the encapsulant extends continuously from the upper surface of the frame to the second step and passes the first step, a space between the first protrusion and the semiconductor chip, and a space between the second protrusion and the semiconductor chip, and
no electrically conductive pattern is disposed directly on the upper surface or the lower surface of each of the first and second protrusions to be electrically connected to the semiconductor chip.
2. The semiconductor package of claim 1 , wherein a region surrounded by the inner wall of the frame in which the first and second protrusions are not formed is filled with a material having rigidity lower than that of the frame.
3. The semiconductor package of claim 2 , wherein the material having rigidity lower than that of the frame is the same as that of the encapsulant.
4. The semiconductor package of claim 1 , wherein the encapsulant has rigidity lower than that of the frame.
5. The semiconductor package of claim 1 , wherein the encapsulant is in contact with the inner wall of the frame.
6. The semiconductor package of claim 1 , wherein the component disposition region has a form of a through hole penetrating through the frame.
7. The semiconductor package of claim 1 , further comprising a conductive via penetrating through the frame.
8. The semiconductor package of claim 1 , wherein the encapsulant covers the frame.
9. The semiconductor package of claim 8 , wherein the encapsulant has an opening exposing a partial region of an upper surface of the frame.
10. The semiconductor package of claim 9 , wherein a conductive pattern is formed on the partial region of the upper surface of the frame and is exposed by the encapsulant.
11. The semiconductor package of claim 1 , wherein a space between the frame and the wiring part is filled with an insulating material.
12. The semiconductor package of claim 11 , further comprising a conductive pattern and a conductive via disposed between the frame and the wiring part and electrically connected to the wiring part.
13. The semiconductor package of claim 1 , further comprising a conductive pattern disposed on the inner wall of the frame.
14. The semiconductor package of claim 1 , wherein each of the first and second protrusions linearly protrudes toward the semiconductor chip.
15. The semiconductor package of claim 1 , the encapsulant is in contact with the upper and lower surfaces of each of the first and second protrusions.
16. The semiconductor package of claim 15 , wherein the encapsulant is in contact with the end surface of each of the first and second protrusions.
17. The semiconductor package of claim 15 , further comprising a conductive pattern disposed on the end surface of each of the first and second protrusions.
18. The semiconductor package of claim 1 , wherein the frame is made of an electrically insulating material.
19. A semiconductor package comprising:
a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer;
a semiconductor chip disposed on the wiring part;
a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the semiconductor chip; and
an encapsulant filling at least a portion of the component disposition region,
wherein a portion of the inner wall of the frame has first and second protrusions protruding toward the semiconductor chip and a recess between the first and second protrusions.
20. The semiconductor package of claim 19 , wherein an upper surface of the frame and an upper surface of the first protrusion are coplanar with each other, and a lower surface of the frame and a lower surface of the second protrusion are coplanar with each other.