IP Library Granted Patent US 10,140,940
Granted Patent B2
US 10,140,940 · App. 15/206,779 · Granted Nov 27, 2018

Display device

Inventor: Yoshiro Aoki (Tokyo, JP)
Assignee: Japan Display Inc.
G09G3/3648G09G3/3614H01L29/786G02F1/1368G02F1/13624G02F2001/13685G09G2300/0852G09G2300/0876G09G2330/023
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Quick Facts
Patent No.
US 10,140,940
App. No.
15/206,779
Granted
Nov 27, 2018
Kind
B2
Abstract

According to one embodiment, a display device has a display area and pixels forming a matrix pattern. Each of the pixels has a display element and a capacitive element series circuit, and a capacitive element series circuit includes a first capacitive element and a second capacitive element. Some switches in a boost control circuit are controlled by a gate signal during one pulse period of an input source signal at least two times. The switches include, a switch being opening and/or closing in a first half of the pulse period, and a switch being closing and/or opening in a second half of the pulse period.

Claims (36)

1. A display device having a display area wherein pixels are arranged in a matrix pattern, each of the pixels comprising:

a display element;

a capacitive element series circuit connected in parallel with the display element, and comprising at least a first capacitive element and a second capacitive element; and

a boost circuit making an electric potential of the capacitive element series circuit increase to obtain a boosted electric potential, and applying the boosted electric potential to the display element,

the boost circuit having a plurality of switches, each controlled in respect of opening and closing by a gate signal during one pulse period of an input source signal, at least one of the switches opening in a first half of the pulse period and closing in a second half of the pulse period, whereas the rest of the switches closing in the first half of the pulse period and opening in the second half of the pulse period.

2. The display device of claim 1 , wherein

the display element controls an image display state upon a voltage signal being given between one terminal and another terminal for the display element,

one terminal of the first capacitive element contained in the capacitive element series circuit is connected to the one terminal of the display element,

one terminal of the first switch included in the boost circuit is connected to the one terminal of the display element,

one terminal of the second switch included in the boost circuit is connected to another terminal of the first capacitive element,

each of another terminals of the first switch and the second switch is connected to a signal line,

one terminal of the second capacitive element contained in the capacitive element series circuit is connected to the aforementioned another terminal of the first capacitive element, moreover, another terminal of the second capacitive element is connected to the aforementioned another terminal of the display element,

one terminal of the third switch included in the boost circuit is connected to the aforementioned another terminal of the first capacitive element, and another terminal of this third switch is connected to the aforementioned another terminal of the display element.

3. The display device of claim 2 , wherein

each of the pixels further has a first gate line and a second gate line,

the first, second, and third switches in each of the pixels are transistors of identical channel type, and

the first and third switches are controlled by a first gate signal from the first gate line, whereas the second switch is controlled by a second gate signal from the second gate line.

4. The display device of claim 2 , wherein

each of the pixels further connected to a corresponding gate line,

the first and third switches in each of the pixels are transistors of identical channel type,

the second switch in each of the pixels is a transistor different in channel type from the first and third switches, and

the first, second and third switches are all controlled by the gate signal from the gate line.

5. The display device of claim 2 , wherein

the first switch is paired with the third switch or, alternatively, the first switch is paired with the second switch, and any of the two transistors paired with each other, one of the transistors is a top-gate type, and the other of the transistors is a bottom-gate type.

6. The display device of claim 5 , wherein

channel portions of transistors of the top-gate type and the bottom-gate type are partly overlapped layer.

7. The display device of claim 2 , wherein

one of electrodes of at least one of the first capacitive element and the second capacitive element has partially more than two transparent electrodes layers.

8. The display device of claim 1 , wherein

the display element in each of the pixels is a liquid-crystal-display element.

9. The display device of claim 1 , wherein

the display element in each of the pixels is an organic EL device.

10. The display device of claim 1 , wherein

the display element in each of the pixels is an organic EL device,

the boost circuit in each of the pixels has a signal input part and drives the organic EL device, and

each of the pixels further has a built-in circuit to supply a control signal to the signal input part of the boost circuit for controlling the organic EL device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2016
From: AOKI, YOSHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 039123/0671 →
Priority Claims (2)
JP 2015-146449 · Jul 24, 2015 · national
JP 2016-014336 · Jan 28, 2016 · national
Continuity (1)
Related Publication 20170025080A1 · Jan 26, 2017
Cited By (5)
US 12,272,700 US 12,282,240 US 12,461,418 US 12,488,767 US 12,512,051