IP Library Granted Patent US 12,282,240
Granted Patent B2
US 12,282,240 · App. 18/368,632 · Granted Apr 22, 2025

Display device and electronic device

Inventors: Susumu Kawashima (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/13624G02F1/136286G02F1/1368H01L27/1225H01L27/1255G09G3/3225G09G3/3266G09G3/3677G09G2300/0426G09G2300/0465G09G2300/0852G09G2310/0286G09G2320/0233G09G2330/021H04N23/57H10K59/1213H10K59/1216
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Quick Facts
Patent No.
US 12,282,240
App. No.
18/368,632
Granted
Apr 22, 2025
Kind
B2
Abstract

A display device capable of improving image quality is provided. A display device includes a plurality of pixel blocks in a display region. The pixel blocks each include a first circuit and a plurality of second circuits. The first circuit has a function of adding a plurality of pieces of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the added data. One pixel has a configuration including one second circuit and an component of the first circuit that is shared. When the first circuit is shared by a plurality of pixels, the aperture ratio can be increased.

Claims (48)

1. A display device comprising:

a source driver;

a first circuit electrically connected to the source driver;

a second circuit electrically connected to the first circuit; and

a third circuit electrically connected to the first circuit,

wherein the first circuit comprises a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to the source driver,

wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the capacitor,

wherein the second circuit comprises a first display element and a third transistor electrically connected to the first display element,

wherein the third circuit comprises a second display element and a fourth transistor electrically connected to the second display element, and

wherein the third transistor and the fourth transistor are electrically connected to the first transistor.

2. The display device according to claim 1 ,

wherein the first transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

3. The display device according to claim 1 ,

wherein the second transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

4. The display device according to claim 1 ,

wherein each of the third transistor and the fourth transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

5. A display device comprising:

a source driver;

a first circuit electrically connected to the source driver;

a second circuit electrically connected to the first circuit; and

a third circuit electrically connected to the first circuit,

wherein the first circuit comprises a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to the source driver,

wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the capacitor,

wherein the second circuit comprises a first light-emitting element and a third transistor electrically connected to the first light-emitting element,

wherein the third circuit comprises a second light-emitting element and a fourth transistor electrically connected to the second light-emitting element, and

wherein the third transistor and the fourth transistor are electrically connected to the first transistor.

6. The display device according to claim 5 ,

wherein the first transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

7. The display device according to claim 5 ,

wherein the second transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

8. The display device according to claim 5 ,

wherein each of the third transistor and the fourth transistor has a channel formation region comprising a metal oxide,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein the element M is selected from the group consisting of Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2023
From: KAWASHIMA, SUSUMU; KUSUMOTO, NAOTO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 064916/0617 →
Priority Claims (1)
JP 2018-085668 · Apr 26, 2018 · national
Continuity (3)
Continuation 17963243 · Oct 11, 2022
Continuation 17047149
Related Publication 20240004248A1 · Jan 4, 2024
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