CMOS image sensor
A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.
1. A method for forming a portion of a CMOS pixel, the method comprising:
forming a first gate electrode by:
forming a first gate insulation layer; and
forming a first polysilicon layer on the first gate insulation layer;
forming a first silicide layer on only a portion of the first polysilicon layer;
forming a first contact on the first silicide layer and above the first silicide layer; and
forming a gate electrode of a drive transistor without a silicide layer above the gate electrode of the drive transistor.
2. The method of claim 1 , wherein said forming a first silicide layer comprises a self-aligned silicide process.
3. The method of claim 1 , wherein the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor.
4. The method of claim 1 , wherein the first gate electrode is formed as a part of a select transistor.
5. The method of claim 1 , further comprising:
forming a second gate electrode by:
forming a second gate insulation layer; and
forming a second polysilicon layer on the second gate insulation layer; and
forming a second silicide layer on only a portion of the second polysilicon layer.
6. The method of claim 5 , wherein said forming a second silicide layer comprises a self-aligned silicide process.
7. The method of claim 5 , wherein:
the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor; and
the second gate electrode is formed as a part of a different one of the select transistor, the transfer transistor, or the reset transistor.
8. The method of claim 7 , wherein the first gate electrode is formed as a part of the select transistor.
9. The method of claim 5 , further comprising:
forming a third gate electrode by:
forming a third gate insulation layer; and
forming a third polysilicon layer on the third gate insulation layer; and
forming a third silicide layer on only a portion of the third polysilicon layer.
10. The method of claim 9 , wherein said forming a third silicide layer comprises a self-aligned silicide process.
11. The method of claim 9 , wherein:
the first gate electrode is formed as a part of one of a select transistor, a transfer transistor, or a reset transistor;
the second gate electrode is formed as a part of a different one of the select transistor, the transfer transistor, or the reset transistor; and
the third gate electrode is formed as a part of the remaining one of the select transistor, the transfer transistor, or the reset transistor.
12. The method of claim 1 , wherein if a voltage is applied at the first contact, the voltage at the contact is greater than a voltage at the first polysilicon layer.
13. The method of claim 12 , wherein a saturation region of a transistor that includes the first gate electrode is expanded in response to a voltage drop across the first polysilicon layer.
14. The method of claim 1 , wherein the first gate electrode is formed as part of a 3-T pixel.
15. The method of claim 1 , wherein the first gate electrode is formed as part of a 4-T pixel.
16. The method of claim 5 , further comprising forming a second contact on the second silicide layer.
17. The method of claim 16 , wherein the second contact is above the second silicide layer.