IP Library Granted Patent US 9,704,784
Granted Patent B1
US 9,704,784 · App. 15/209,964 · Granted Jul 11, 2017

Method of integrating a copper plating process in a through-substrate-via (TSV) on CMOS wafer

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Quick Facts
Patent No.
US 9,704,784
App. No.
15/209,964
Granted
Jul 11, 2017
Kind
B1
Abstract

A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.

Claims (29)

1. A method of forming a through-substrate-via (TSV) interconnect in a semiconductor substrate, comprising:

providing a semiconductor substrate having a front surface and a back surface, and comprising a metallization structure at the front surface, and an active device layer within the semiconductor substrate and adjacent to the metallization structure, the metallization structure comprising a landing pad comprising a conductive metal layer interposed between first and second barrier layers;

forming a through-substrate-via (TSV) through the semiconductor substrate from the back surface through the active device layer and the first barrier layer to expose the conductive metal layer of the landing pad;

removing the conductive metal layer of the landing pad to extend the through-substrate-via (TSV) by a space within the metallization structure and expose the second barrier layer; and

filling the through-substrate-via (TSV) including the space with copper to form the TSV interconnect.

2. The method of claim 1 , wherein filling the TSV including the space with copper comprises forming a diffusion barrier layer and optionally a seed layer over exposed surfaces of the TSV including the space, and conducting a copper plating process, and

the metal layer of the landing pad comprises a metal that is incompatible with the diffusion barrier layer, the optional seed layer and the copper plating chemistry such that the diffusion barrier layer, seed layer and copper do not form a coating over any residual portion of the metal layer and a gap or void is present between any residual portion of the metal layer and the copper.

3. The method of claim 2 , wherein the metal layer of the landing pad comprises aluminum.

4. A method of forming a through-substrate-via (TSV) interconnect in a semiconductor substrate, comprising:

providing a device wafer having a front surface and a back surface, a metallization structure at the front surface, and an active device layer within the semiconductor substrate and adjacent to the metallization structure, the metallization structure comprising a landing pad comprising an aluminum layer interposed between a first and a second Ti/TiN barrier layer,

dry etching to form a through-substrate-via (TSV) through the device wafer from the back surface through the active device layer and the first Ti/TiN barrier layer to expose the aluminum layer of the landing pad;

wet etching to remove the aluminum layer to extend the through-substrate-via (TSV) to an exposed surface of the second Ti/TiN layer; and

filling the through-substrate-via (TSV) with copper by an electroplating process to form the TSV interconnect.

5. The method of claim 4 , wherein the step of dry etching to form the through-substrate-via (TSV) comprises at least one of plasma etching, reactive ion etching (RIE), ion beam etching, magnetically enhanced RIE, inductively coupled plasma (ICP), and laser drilling.

6. The method of claim 4 , wherein the step of wet etching to remove the aluminum layer comprises applying a Standard Clean (SC-1) solution, and aluminum etchant solution, or a combination thereof.

7. The method of claim 4 , wherein the step of wet etching to remove the aluminum layer comprises applying a Standard Clean (SC-1) solution comprising an aqueous solution of hydrogen peroxide (H 2 O 2 ) and ammonium hydroxide (NH 4 OH).

8. The method of claim 7 , wherein the Standard Clean (SC-1) solution comprises a mixture of water, aqueous hydrogen peroxide (30% by weight) and aqueous ammonium hydroxide (29% by weight of NH 3 ) in a ratio (H 2 O:H 2 O 2 :NH 4 O) of 20 to 5:1 to 1:1 to 1, by volume.

9. The method of claim 7 , wherein the Standard Clean (SC-1) solution is applied at a temperature of 40 to 50° C.

10. The method of claim 4 , wherein the step of wet etching to remove the aluminum layer comprises applying an aluminum etchant solution comprising an aqueous mixture of phosphoric acid, nitric acid, acetic acid and water at a ratio (H 3 PO 4 :HNO 3 :CH 3 COOH:H 2 O) of 80:5:5:10 by volume.

11. The method of claim 10 , wherein the aluminum etchant solution comprise 65 to 80% phosphoric acid (H 3 PO 4 ), 1 to 5% nitric acid (HNO 3 ), 5 to 10% acetic acid (CH 3 COOH) and the balance water.

12. The method of claim 10 , wherein the aluminum etchant solution is applied at a temperature of 35-45° C.

13. The method of claim 4 , wherein all of the aluminum layer is removed by the step of wet etching.

14. The method of claim 4 , wherein after the step of wet etching, a residual portion of the aluminum layer remains.

15. The method of claim 14 , wherein a gap is present between the copper fill and the residual portion of the aluminum layer.

16. The method of claim 4 , wherein the step of filling the through-substrate-via (TSV) comprises:

optionally applying an activation composition to exposed surfaces of the TSV to form an activated surface;

forming a diffusion barrier layer over the exposed surfaces and optionally the activated surface;

optionally forming a seed layer over the diffusion barrier layer; and

depositing copper to fill the through-substrate-via (TSV) by an electrochemical deposition process.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2016
From: LAGOUGE, MATTHIEU; ZHANG, QING; CHOUDHURI, MOHOMMAD; ZEB, GUL
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 039338/0907 →