IP Library Granted Patent US 9,704,867
Granted Patent B2
US 9,704,867 · App. 15/219,922 · Granted Jul 11, 2017

Dual fin integration for electron and hole mobility enhancement

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,704,867
App. No.
15/219,922
Granted
Jul 11, 2017
Kind
B2
Abstract

A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Claims (5)

1. A semiconductor device comprising:

trapezoidal shaped fins formed on a substrate, wherein a trapezoidal shape of the trapezoidal shaped fins enhances electron mobility; and

vertical shaped fins formed on the substrate, wherein a straight vertical shape of the vertical shaped fins enhances hole mobility, wherein the trapezoidal shaped fins have a larger base that the vertical shaped fins;

wherein the trapezoidal shaped fins and the vertical shaped fins are formed together as components in an integrated circuit.

2. The semiconductor device of claim 1 , wherein the integrated circuit having both the trapezoidal shaped fins and the vertical shaped fins is a microprocessor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2021
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: HFC SEMICONDUCTOR CORPORATION
Reel/Frame 055614/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: CHEN, CHIA-YU; LIU, ZUOGUANG; WANG, MIAOMIAO; YAMASHITA, TENKO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039261/0494 →