Semiconductor package structure and method for manufacturing the same
View Patent ↗A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n≧1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.
1. A method for manufacturing a semiconductor package structure, comprising:
attaching a substrate to a carrier, the substrate having a first side, a second side and an opening extending from the first side to the second side, wherein the substrate comprises a redistribution layer and a via; and
attaching a die stack of n die(s) to the carrier through the opening, wherein n≧1;
wherein the thickness of the substrate is substantially the same as the thickness of the die stack, and the redistribution layer and the via do not overlap with the die stack in a top view.
2. The method according to claim 1 , wherein the substrate is a wafer or a panel.
3. The method according to claim 1 , wherein one of the n dies is different from another one of the n dies.
4. The method according to claim 1 , further comprising:
forming a first adhesive insulating layer on the first side of the substrate and between the substrate and the die stack; and
removing the carrier.
5. The method according to claim 4 , further comprising:
forming a second adhesive insulating layer on the second side of the substrate.
6. The method according to claim 5 , wherein the first adhesive insulating layer and the second adhesive insulating layer comprise a light-sensitive adhesive.
7. The method according to claim 5 , further comprising:
forming at least one first circuit layer on the first side of the substrate, the at least one first circuit layer comprising pads; and
forming at least one second circuit layer on the second side of the substrate, the at least one second circuit layer comprising pads.
8. The method according to claim 7 , wherein the at least one first circuit layer and the at least one second circuit layer are formed by semi-additive metallization process.
9. The method according to claim 7 , further comprising:
forming a first passivation layer on the at least one first circuit layer, the first passivation layer exposing the pads of the at least one first circuit layer; and
forming a second passivation layer on the at least one second circuit layer, the second passivation layer exposing the pads of the at least one second circuit layer.
10. The method according to claim 9 , further comprising:
providing a die on the first passivation layer and electrically connecting the die provided on the first passivation layer to the pads of the at least one first circuit layer.
11. The method according to claim 10 , wherein the die provided on the first passivation layer is electrically connected to the pads of the at least one first circuit layer by wire bonding, ball grid array bonding or flip chip bonding.
12. The method according to claim 4 , further comprising:
cutting the substrate.