Method for wafer level reliability

1. A method for ensuring wafer level reliability, comprising:

forming a trench on a semiconductor substrate;

forming a sidewall oxide layer and a liner nitride layer on the trench;

filling an insulating material on the liner nitride layer;

forming a PMOS element on the semiconductor substrate; and

assessing hot electron induced punch through (HEIP) for the PMOS element at a condition of gate and drain voltages satisfying Vg=Vd, wherein Vg is the gate voltage and Vd is the drain voltage.

2. The method of claim 1 , wherein the assessing of the HEIP is implemented based on a threshold voltage (Vth) shift ratio being determined to be less than 10%.

3. The method of claim 1 , further comprising assessing a negative bias temperature instability (NBTI) for the PMOS element.

4. The method of claim 1 , further comprising assessing a PMOS HCl test for the PMOS element at a condition of gate and drain voltages satisfying Vg=Vd.

5. The method of claim 4 , wherein the drain voltage satisfies Vd=Vop,max×1.1, wherein Vop,max is a maximum operation voltage.

6. A method for ensuring wafer level reliability, the method comprising:

determining whether a semiconductor element to be formed is a PMOS element or an NMOS element; and

in response to a determination that the semiconductor element is a PMOS element, performing HEIP and NBTI tests, or a PMOS HCl test,

wherein the HEIP test is implemented based on a threshold voltage (Vth) shift ratio being determined to be less than 10%.

7. The method of claim 6 , wherein the determining of whether the semiconductor element to be formed is the PMOS element or the NMOS element further involves determining whether the semiconductor element is a high voltage NMOS element; and

in response to a determination that the semiconductor element is a high voltage NMOS element, performing a sub-HCl test.

8. The method of claim 6 , wherein the determining of whether the semiconductor element to be formed is the PMOS element or the NMOS element further involves determining whether the semiconductor element is a low voltage PMOS element; and

in response to a determination that the semiconductor element is a low voltage PMOS element, the PMOS HCl test is performed.

9. The method of claim 6 , wherein the performing of the HEIP test is implemented at a condition of gate and drain voltages satisfy Vg=Vd, wherein Vg is the gate voltage and Vd is the drain voltage.

10. The method of claim 6 , wherein the performing of the PMOS HCl test is implemented at a condition of gate and drain voltages satisfy Vg=Vd, wherein Vg is the gate voltage and Vd is the drain voltage.

11. The method of claim 10 , wherein the drain voltage satisfies Vd=Vop,max×1.1, wherein Vop,max is a maximum operation voltage.

12. A method for ensuring wafer level reliability, the method comprising:

determining whether a semiconductor element to be formed is a PMOS element or an NMOS element; and

in response to a determination that the semiconductor element is a PMOS element, performing hot electron induced punch through (HEIP) and negative bias temperature instability (NBTI) tests,

wherein the PMOS element comprises:

a trench formed on a semiconductor substrate;

a sidewall oxide layer and a liner nitride layer formed on the trench; and

an insulating material formed on the liner nitride layer, and

wherein the HEIP test is implemented based on a threshold voltage (Vth) shift ratio being changed to a negative value.

13. The method of claim 12 , wherein a PMOS HCl test is performed in response to the determination that the semiconductor element is a PMOS element.

14. The method of claim 12 , wherein the HEIP test is implemented based on a threshold voltage (Vth) shift ratio being determined to be less than 10%.

15. The method of claim 12 , wherein the performing of the HEIP test is implemented at a condition of gate and drain voltages satisfy Vg=Vd, wherein Vg is the gate voltage and Vd is the drain voltage.