Semiconductor memory device including an asymmetrical memory core region
According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.
1. A semiconductor memory device comprising:
a substrate;
a plurality of first control gate electrodes arranged in a first direction and extending in a second direction and a third direction, the first direction intersecting with the substrate, the second direction intersecting with the first direction, and the third direction intersecting with the first direction and the second direction;
a plurality of second control gate electrodes arranged in the first direction and extending in the second direction and the third direction, the plurality of second control gate electrodes being provided between the plurality of the first control gate electrodes and the substrate;
a memory string including a plurality of memory cells and a dummy cell connected to the memory cell in series;
a select gate transistor connected to the memory string, one of the plurality of first control gate electrodes being a gate of the select gate transistor; and
a memory pillar extending in the first direction, the memory pillar including a core insulating layer extending in the first direction, a semiconductor layer arranged between the core insulating layer and the plurality of the first control gate electrodes and between the core insulating layer and the plurality of the second control gate electrodes, and a charge accumulation layer arranged between the semiconductor layer and one of the first control gate electrodes and the plurality of second control gate electrodes, wherein
the semiconductor layer includes a first portion and a second portion, the second portion being provided between the first portion and the substrate,
the first portion extends in the first direction, and includes a first surface and a second surface in the second direction or the third direction, the first surface facing the plurality of the first control gate electrodes in the second direction or the third direction, and the second surface being connected to the core insulating layer,
the second portion extends in the first direction, and includes a third surface and a fourth surface, the third surface facing the plurality of the second control gate electrodes in the second direction or the third direction, and the fourth surface being connected to the core insulating layer,
a distance between the first surface and the second surface of the first portion of the semiconductor layer in the second direction or the third direction at a position of the select gate transistor is larger than a distance between the third surface and the fourth surface of the second portion of the semiconductor layer in the second direction or the third direction,
the core insulating layer includes a third portion and a fourth portion,
the third portion is provided on the second surface of the first portion of the semiconductor layer,
the fourth portion is provided on the fourth surface of the second portion of the semiconductor layer, and
a width in the second direction or the third direction of the fourth portion of the core insulating layer is larger than a width in the second direction or the third direction of the third portion of the core insulating layer.
2. The semiconductor memory device according to claim 1 , wherein
an end in the first direction of the first portion of the semiconductor layer and an end in the first direction of the third portion of the core insulating layer are connected to an end in the first direction of the fourth portion of the core insulating layer.
3. The semiconductor memory device according to claim 1 , wherein
at least one of the plurality of the memory cells corresponds to: one of the plurality of the second control gate electrodes; a part of the second portion of the semiconductor layer; and a part of the charge accumulation layer, and
the dummy cell corresponds to: one of the plurality of the first control gate electrodes; and at least a part of the first portion of the semiconductor layer.