Methods and circuits for asymmetric distribution of channel equalization between devices
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
1. A memory system comprising:
a signal lane to convey a first signal in a first direction at a symbol rate and a second signal in a second direction opposite the first direction at the symbol rate;
a memory-buffer integrated-circuit (IC) having:
a first transmitter coupled to the signal lane, the first transmitter to transmit the first signal over the signal lane; and
a first receiver having a first receive equalizer coupled to the signal lane to receive the second signal, the second signal exhibiting a first signal-to-ISI ratio (SIR) at the memory-buffer IC; and
a memory IC having;
a second transmitter coupled to the signal lane to transmit the second signal to the first receiver; and
a second receiver coupled to the signal lane to receive the first signal from the first transmitter, the first signal exhibiting a second SIR at the memory IC;
wherein the first SIR is a least 30% lower than the second SIR.
2. The memory system of claim 1 , wherein the first transmitter includes a first transmit equalizer that supports a first number of filter coefficients and the second transmitter includes a second transmit equalizer that supports a second number of filter coefficients, wherein the first number of filter coefficients is greater than the second number of filter coefficients.
3. The memory system of claim 2 , wherein the first receiver supports a third number of filter coefficients and the second receiver supports a fourth number of filter coefficients, wherein the third number of filter coefficients is greater than the fourth number of filter coefficients.
4. The memory system of claim 1 , wherein the signal lane comprises a bidirectional channel extending between the memory-buffer IC and the memory IC.
5. The memory system of claim 1 , wherein the signal lane comprises first and second unidirectional communication channels extending between the memory-buffer IC and the memory IC.
6. The memory system of claim 1 , further comprising a third IC having:
a third transmitter coupled to the signal lane; and
a third receiver coupled to the signal lane.
7. The memory system of claim 6 , the memory-buffer IC having:
a first memory to store a first set of filter coefficients for communication with the memory IC; and
a second memory to store a first set of filter coefficients for communication with the third IC.
8. The memory system of claim 1 , wherein the memory-buffer IC comprises a memory controller and the memory IC comprises memory.
9. The memory system of claim 1 , wherein the first transmitter includes a finite impulse response equalizer.
10. The memory system of claim 1 , wherein the first receiver includes at least one of a decision feedback equalizer, a partial-response decision feedback equalizer, and a continuous time linear equalizer.
11. The memory system of claim 1 , wherein the first transmitter includes a transmit equalizer to provide a DC offset to the first signal.
12. The memory system of claim 1 , wherein the first receiver includes a receive equalizer to provide a DC offset to the second signal.
13. The memory system of claim 1 , wherein the first receiver includes a first filter-coefficient port to receive receiver filter coefficients and the first transmitter includes a second filter-coefficient port to receive transmitter filter coefficients.
14. The memory system of claim 13 , wherein the memory-buffer IC further comprises equalization control circuitry adapted to derive the transmitter filter coefficients from the second signal.
15. The memory system of claim 14 , wherein the equalization control circuitry is adapted to derive the transmitter filter coefficients from the receiver filter coefficients.
16. The memory system of claim 1 , wherein the memory-buffer IC has a first number of interconnect layers and the memory IC has a second number of interconnect layers, wherein the first number is at least twice the second number.
17. The memory system of claim 1 , wherein the memory-buffer IC further comprises a transmit equalizer having an equalizer control port to receive filter coefficients and equalization control circuitry coupled to the equalizer control port, wherein the equalization control circuitry derives transmitter filter coefficients from the second signal.
18. A method comprising:
equalizing, at a memory-buffer IC, a first signal using a first transmit coefficient;
transmitting the equalized first signal from the memory-buffer IC;
receiving at the memory-buffer IC a corrupted second signal from a memory IC, where the corrupted second signal includes corruption in a form of inter-symbol interference;
measuring the corruption of the corrupted second signal;
deriving a second transmit coefficient from the measured corruption; and
equalizing, at the memory-buffer IC, the first signal using the second transmit coefficient.
19. The method of claim 18 , further comprising deriving a receive coefficient from the corruption and equalizing, at the memory-buffer IC, the corrupted second signal using the receive coefficient.
20. The method of claim 19 , wherein the second transmit coefficient is calculated from the receive coefficient.