Packaged semiconductor chips having heat dissipation layers and ground contacts therein
Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.
1. A semiconductor package, comprising:
a package substrate comprising a top surface and a bottom surface facing each other and a ground pad on the top surface of the package substrate;
a semiconductor chip mounted on the top surface of the package substrate, the semiconductor chip comprising a bottom surface facing the top surface of the package substrate and a top surface that is opposite the bottom surface thereof;
a mold layer lying on the top surface of the package substrate to enclose the semiconductor chip and having a top surface that is coplanar with the top surface of the semiconductor chip; and
a heat dissipation layer provided on the semiconductor chip and the mold layer,
wherein the heat dissipation layer is in direct contact with the top surface of the semiconductor chip and the top surface of the mold layer and comprises a ground contact that passes through the mold layer and is electrically connected to the ground pad, and
the top surface of the semiconductor chip has a surface roughness that is smaller than a surface roughness of the top surface of the mold layer.
2. The semiconductor package of claim 1 , wherein the heat dissipation layer comprises:
a bottom surface that is in direct contact with the top surface of the semiconductor chip and the top surface of the mold layer; and
a top surface that is opposite the bottom surface thereof,
wherein the top surface of the heat dissipation layer is uneven.
3. The semiconductor package of claim 1 , wherein the heat dissipation layer has a uniform thickness on the top surface of the package substrate.
4. The semiconductor package of claim 1 , wherein the heat dissipation layer has a non-uniform thickness on the top surface of the package substrate.
5. The semiconductor package of claim 1 , wherein the heat dissipation layer completely covers the top surfaces of the semiconductor chip and the mold layer.
6. The semiconductor package of claim 1 , wherein the heat dissipation layer covers a portion of the top surface of the semiconductor chip and a portion of the top surface of the mold layer.