Semiconductor package and manufacturing method of the same
The present disclosure provides a semiconductor package, including a first semiconductor die layer having an active surface, a conductive contact electrically coupled to the active surface, a sidewall of the conductive contact being surrounded by an insulating layer, and a solder bump connected to the conductive contact. A seed layer is between the sidewall of the conductive contact and the insulating layer. The present disclosure provides a method for manufacturing a semiconductor package, the method including providing a carrier, forming an insulating layer over the carrier, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation.
1. A semiconductor package, comprising:
a first semiconductor die layer having a first surface and a second surface opposite to the first surface;
a conductive contact electrically coupled to the first surface, a sidewall of the conductive contact being surrounded by an insulating layer disposed over the second surface of the first semiconductor die layer, a width of the conductive contact in proximity to the second surface being narrower than a width of the conductive contact in proximity to the first surface; and
a solder bump connected to the conductive contact,
wherein a seed layer is between the sidewall of the conductive contact and the insulating layer.
2. A semiconductor package, comprising:
a first semiconductor die layer having an active surface;
a conductive contact electrically coupled to the active surface, a sidewall of the conductive contact being surrounded by an insulating layer; and
a solder bump connected to the conductive contact,
wherein a seed layer is between the sidewall of the conductive contact and the insulating layer, and wherein the conductive contact further comprises a mesa protruding from the insulating layer and being connected to the solder bump.
3. The semiconductor package of claim 2 , wherein the conductive contact comprises a via of a redistribution layer (RDL).
4. The semiconductor package of claim 3 , wherein the solder bump is closer to the active surface than a passive surface of the first semiconductor die layer.
5. The semiconductor package of claim 2 , wherein the conductive contact comprises a through insulator via (TIV).
6. The semiconductor package of claim 5 , further comprising a second semiconductor die layer electrically coupled to the conductive contact through the solder bump over a passive surface of the first semiconductor die layer.
7. The semiconductor package of claim 6 , wherein the second semiconductor die layer comprises a dynamic random access memory (DRAM).
8. The semiconductor package of claim 2 , wherein the sidewall comprises a tapered shape.
9. The semiconductor package of claim 2 , wherein first semiconductor die layer comprises a silicon-on-chip (SOC) die.
10. The semiconductor package of claim 2 , further comprising a ball grid array (BGA) closer to the active surface than a passive surface of the first semiconductor die layer.
11. The semiconductor package of claim 2 , wherein a portion of the mesa protruding from the insulating layer is not surrounded by the seed layer between the sidewall of the conductive contact and the insulating layer.
12. A semiconductor package, comprising:
a semiconductor die layer having an active surface;
a through insulator via (TIV) electrically coupled to the active surface, the TIV comprising:
a body surrounded by molding compound; and
a mesa having a tapered sidewall over the body and surrounded by an insulating layer overlaying the molding compound; and
a solder bump directly in contact with-the mesa of the TIV.
13. The semiconductor package of claim 12 , further comprising a seed layer between the tapered sidewall and the insulating layer.
14. The semiconductor package of claim 12 , wherein a portion of the tapered sidewall protrudes from the insulating layer.
15. The semiconductor package of claim 14 , wherein a height of the portion of the tapered sidewall protruding from the insulating layer is from about 1 μm to about 7 μm.
16. The semiconductor package of claim 12 , wherein the TIV is electrically coupled to the active surface of the semiconductor die layer through connection of the body and a redistribution layer (RDL).
17. A semiconductor package, comprising:
a semiconductor die having an active surface;
a redistribution layer (RDL) electrically coupled to the active surface, the RDL comprising:
a conductive line surrounded by a dielectric layer; and
a conductive via surrounded by the dielectric layer, the conductive via comprising a tapered sidewall a horizontal surface, the horizontal surface being exposed from the dielectric layer; and
a seed layer between the tapered sidewall and the dielectric layer.
18. The semiconductor package of claim 17 , wherein a portion of the tapered sidewall is protruding from the dielectric layer.
19. The semiconductor package of claim 18 , further comprising a first solder bump contacting the horizontal surface and the portion of the tapered sidewall.
20. The semiconductor package of claim 17 , wherein the RDL is electrically coupled to the active surface through a second solder bump.