Semiconductor wafer and method of ball drop on thin wafer with edge support ring
A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer;
forming a conductive layer over a surface of the semiconductor wafer within the edge support ring;
providing a first stencil including a plurality of first openings, wherein the first stencil includes a horizontal portion with a notch and a portion of the edge support ring is disposed within the notch to extend the first openings of the first stencil to the conductive layer;
disposing the first stencil over the edge support ring with the first openings extending to and aligned with the conductive layer; and
dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer.
2. The method of claim 1 , wherein the horizontal portion of the first stencil extends over the edge support ring, and a step-down portion extends the first openings of the first stencil to the conductive layer.
3. The method of claim 1 , wherein the first stencil includes a vertical extension from the horizontal portion to the semiconductor wafer.
4. The method of claim 1 , further including:
removing the first stencil; and
bonding the bumps to the conductive layer.
5. The method of claim 1 , further including:
providing a second stencil including a plurality of second openings;
disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and
depositing a flux material in the second openings over the conductive layer.
6. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer within the edge support ring, wherein the edge support ring extends above the surface of the semiconductor wafer;
disposing a first stencil over the edge support ring, wherein the first stencil includes a vertical portion extending from the edge support ring down to the surface of the semiconductor wafer to place a plurality of first openings in the first stencil in proximity to and aligned with the conductive layer, wherein the first stencil includes a horizontal portion over the edge support ring, and the vertical portion includes a step-down portion extending the first openings of the first stencil to the conductive layer; and
dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer.
7. The method of claim 6 , further including:
removing the first stencil; and
bonding the bumps to the conductive layer.
8. The method of claim 6 , further including:
disposing a second stencil over the edge support ring with a plurality of second openings extending to and aligned with the conductive layer; and
depositing a flux material in the second openings over the conductive layer.
9. The method of claim 8 , wherein the second stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the second openings of the second stencil to the conductive layer.
10. The method of claim 8 , wherein the second stencil includes a sloped surface extending the second openings of the second stencil to the conductive layer.
11. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer within the edge support ring, wherein the edge support ring extends above the surface of the semiconductor wafer;
disposing a first stencil over the edge support ring, wherein the first stencil includes a vertical portion extending from the edge support ring down to the surface of the semiconductor wafer to place a plurality of first openings in the first stencil in proximity to and aligned with the conductive layer, wherein the first stencil includes a horizontal portion with a notch, and a portion of the edge support ring is disposed within the notch to extend the first openings to the conductive layer; and
dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer.
12. A semiconductor wafer, comprising:
a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer within the edge support ring;
a first stencil disposed over the edge support ring, wherein the first stencil includes a vertical portion extending from the edge support ring down to the surface of the semiconductor wafer to place a plurality of first openings in the first stencil in proximity to and aligned with the conductive layer, wherein the first stencil includes a horizontal portion over the edge support ring, and the vertical portion includes a step-down portion extending the first openings of the first stencil to the conductive layer; and
a plurality of bumps dispersed over the first stencil to occupy the first openings over the conductive layer.
13. The semiconductor wafer of claim 12 , wherein the bumps are bonded to the conductive layer.
14. The semiconductor wafer of claim 12 , further including:
a second stencil over the edge support ring with a plurality of second openings extending to and aligned with the conductive layer; and
a flux material deposited in the second openings over the conductive layer.
15. The semiconductor wafer of claim 14 , wherein the second stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the second openings of the second stencil to the conductive layer.
16. The semiconductor wafer of claim 14 , wherein the second stencil includes a sloped surface extending the second openings of the second stencil to the conductive layer.
17. A semiconductor wafer, comprising:
a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer within the edge support ring;
a first stencil disposed over the edge support ring, wherein the first stencil includes a vertical portion extending from the edge support ring down to the surface of the semiconductor wafer to place a plurality of first openings in the first stencil in proximity to and aligned with the conductive layer, wherein the first stencil includes a horizontal portion with a notch, and a portion of the edge support ring is disposed within the notch to extend the first openings to the conductive layer; and
a plurality of bumps dispersed over the first stencil to occupy the first openings over the conductive layer.