IP Library Granted Patent US 9,685,337
Granted Patent B2
US 9,685,337 · App. 15/243,986 · Granted Jun 20, 2017

Method for fabricating semiconductor device

Inventors: Ching-Wen Hung (Tainan, TW); Jia-Rong Wu (Kaohsiung, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Chih-Sen Huang (Tainan, TW); Chun-Hsien Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/28123H01L21/28088H01L21/28518H01L21/76805H01L21/76843H01L21/76895H01L29/0653H01L29/4966H01L29/66545H01L29/66795H01L29/7851H01L29/665
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Quick Facts
Patent No.
US 9,685,337
App. No.
15/243,986
Granted
Jun 20, 2017
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Claims (30)

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a fin-shaped structure on the substrate and a shallow trench isolation (STI) around the fin-shaped structure;

forming a first gate structure on the substrate;

forming a first contact plug adjacent to the first gate structure and a second contact plug on the STI;

removing the second contact plug on the STI; and

performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate after forming the first contact plug.

2. The method of claim 1 , further comprising:

forming the first gate structure on the substrate and a second gate structure on the STI, wherein the first gate structure comprises a first hard mask and the second gate structure comprises a second hard mask;

forming a first spacer adjacent to the first gate structure and a second spacer adjacent to the second gate structure;

forming a first contact plug contacting the first spacer and forming the second contact plug on the STI and contacting the second spacer;

forming a third hard mask on the first gate structure and the first contact plug;

removing the second contact plug to form a first recess;

forming an interlayer dielectric (ILD) layer in the first recess;

removing part of the first contact plug;

forming a fourth hard mask on the first contact plug; and

performing the RMG process.

3. The method of claim 2 , wherein the third hard mask and the fourth hard mask comprise same material.

4. The method of claim 2 , further comprising:

forming a source/drain region in the substrate and adjacent to the first gate structure;

forming silicide layer on the source/drain region;

forming a metal layer on the fin-shaped structure, the STI, the first gate structure, and the second gate structure; and

planarizing the metal layer to form the first contact plug and the second contact plug.

5. The method of claim 2 , wherein the RMG process further comprises:

removing the first gate structure and the second gate structure to form a second recess on the fin-shaped structure and a third recess on the STI;

forming a work function metal layer and a low resistance metal layer in the second recess and the third recess;

planarizing the low resistance metal layer and the work function metal layer to form a first metal gate on the fin-shaped structure and a second metal gate on the STI; and

forming a fifth hard mask on the first metal gate and a sixth hard mask on the second metal gate.

6. The method of claim 5 , wherein the top surfaces of the fourth hard mask and the fifth hard mask are coplanar.

7. The method of claim 5 , wherein the fourth hard mask and the fifth hard mask comprise different material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2016
From: HUNG, CHING-WEN; WU, JIA-RONG; LEE, YI-HUI; LIU, YING-CHENG; HUANG, CHIH-SEN; LIN, CHUN-HSIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 039501/0923 →
Priority Claims (1)
TW 104132992 A · Oct 7, 2015 · national
Continuity (2)
Division 14935456 · Nov 9, 2015
Related Publication 20170103896A1 · Apr 13, 2017