Semiconductor device including an oxide semiconductor
View Patent ↗A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.
1. A semiconductor device comprising:
a first transistor comprising a channel formation region including a silicon;
an insulating layer over the first transistor; and
a second transistor over the insulating layer,
wherein the second transistor comprising:
a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a gate insulating layer over the third oxide semiconductor layer, and
a gate electrode over the gate insulating layer,
wherein a content of indium in the second oxide semiconductor layer is higher than a content of indium in the first oxide semiconductor layer,
wherein the content of indium in the second oxide semiconductor layer is higher than a content of indium in the third oxide semiconductor layer,
wherein the second oxide semiconductor layer has higher conductivity than the third oxide semiconductor layer and the first oxide semiconductor layer, and
wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
2. A semiconductor device comprising:
a first transistor comprising a channel formation region including a silicon;
an insulating layer over the first transistor; and
a second transistor over the insulating layer,
wherein the second transistor comprising:
a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a gate insulating layer over the third oxide semiconductor layer, and
a gate electrode over the gate insulating layer,
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein the content of the indium in the second oxide semiconductor layer is higher than a content of the zinc in the second oxide semiconductor layer,
wherein the second oxide semiconductor layer has higher conductivity than the third oxide semiconductor layer and the first oxide semiconductor layer, and
wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
3. The semiconductor device according to claim 1 ,
wherein the side surface of the first oxide semiconductor layer is tapered, and
wherein the side surface of the second oxide semiconductor layer is tapered.
4. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.
5. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.
6. The semiconductor device according to claim 1 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.
7. The semiconductor device according to claim 6 , further comprising a capacitor comprising the source electrode layer and the gate insulating layer.
8. The semiconductor device according to claim 1 ,
further comprising a conductive layer between the first transistor and the first oxide semiconductor layer, and
wherein the conductive layer is overlapped with the second oxide semiconductor layer.
9. The semiconductor device according to claim 2 ,
wherein the side surface of the first oxide semiconductor layer is tapered, and
wherein the side surface of the second oxide semiconductor layer is tapered.
10. The semiconductor device according to claim 2 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.
11. The semiconductor device according to claim 2 , wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.
12. The semiconductor device according to claim 2 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.
13. The semiconductor device according to claim 12 , further comprising a capacitor comprising the source electrode layer and the gate insulating layer.
14. The semiconductor device according to claim 2 ,
further comprising a conductive layer between the first transistor and the first oxide semiconductor layer, and
wherein the conductive layer is overlapped with the second oxide semiconductor layer.
15. A semiconductor device comprising:
a first transistor comprising a channel formation region including a silicon;
an insulating layer over the first transistor; and
a second transistor over the insulating layer,
wherein the second transistor comprising:
a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer; and
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer,
wherein a content of indium in the second oxide semiconductor layer is higher than a content of indium in the first oxide semiconductor layer,
wherein the content of indium in the second oxide semiconductor layer is higher than a content of indium in the third oxide semiconductor layer, and
wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
16. A semiconductor device comprising:
a first transistor comprising a channel formation region including a silicon;
an insulating layer over the first transistor; and
a second transistor over the insulating layer,
wherein the second transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer; and
a third oxide semiconductor layer over the second oxide semiconductor layer,
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein the content of the indium in the second oxide semiconductor layer is higher than a content of the zinc in the second oxide semiconductor layer, and
wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
17. The semiconductor device according to claim 16 , wherein the side surface of the first oxide semiconductor layer is tapered, and wherein the side surface of the second oxide semiconductor layer is tapered.
18. The semiconductor device according to claim 15 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.
19. The semiconductor device according to claim 17 ,
wherein the side surface of the first oxide semiconductor layer is tapered, and
wherein the side surface of the second oxide semiconductor layer is tapered.
20. The semiconductor device according to claim 16 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.