Granted Patent B2

US 12,363,953 · App. 17/883,683 · Granted Jul 15, 2025

Inventor: Shunpei Yamazaki (Tokyo, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10D30/6755H10D30/615H10D30/67H10D30/6757H10D62/80

Abstract

Claims (26)

1. A semiconductor device comprising:

a first oxide semiconductor layer comprising indium and gallium, the first oxide semiconductor layer comprising a channel formation region;

a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;

a gate insulating layer comprising silicon over the second oxide semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein a content of the indium in the first oxide semiconductor layer is higher than a content of the gallium in the first oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and comprises an impurity element, and

wherein the second oxide semiconductor layer covers a side surface and a top surface of the first oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the impurity element is at least one of phosphorus, boron, nitrogen, arsenic, argon, and aluminum.

3. The semiconductor device according to claim 1 , further comprising a third oxide semiconductor layer under the first oxide semiconductor layer.

4. The semiconductor device according to claim 3 , wherein the third oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer and the second oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the side surface of the first oxide semiconductor layer is tapered.

6. A semiconductor device comprising:

a first oxide semiconductor layer comprising indium, gallium, and zinc, the first oxide semiconductor layer comprising a channel formation region;

a second oxide semiconductor layer comprising indium, gallium, and zinc over the first oxide semiconductor layer;

a gate insulating layer comprising silicon over the second oxide semiconductor layer;

a gate electrode over the gate insulating layer; and

a source electrode and a drain electrode which are in contact with the second oxide semiconductor layer,

wherein a content of the indium in the first oxide semiconductor layer is higher than a content of the gallium in the first oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and comprises an impurity element,

wherein the second oxide semiconductor layer covers a side surface and a top surface of the first oxide semiconductor layer, and

wherein the source electrode and the drain electrode are not in contact with the first oxide semiconductor layer.

7. The semiconductor device according to claim 6 , wherein the impurity element is at least one of phosphorus, boron, nitrogen, arsenic, argon, and aluminum.

8. The semiconductor device according to claim 6 , further comprising a third oxide semiconductor layer under the first oxide semiconductor layer.

9. The semiconductor device according to claim 8 , wherein the third oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer and the second oxide semiconductor layer.

10. The semiconductor device according to claim 6 , wherein the side surface of the first oxide semiconductor layer is tapered.

Assignments (1)

Priority Claims (2)

Continuity (7)

References Cited (400)