IP Library › Granted Patent US 8,278,162
Granted Patent B2
US 8,278,162 · App. 12/768,205 · Granted Oct 2, 2012

Method for manufacturing semiconductor device

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,278,162
App. No.
12/768,205
Granted
Oct 2, 2012
Kind
B2
Abstract

A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

Claims (43)

1. A method for manufacturing a semiconductor device comprising:

forming a first conductive layer over an insulating surface;

performing a first patterning to form a first gate electrode;

forming a first insulating film over the first gate electrode;

forming a second conductive layer over the first insulating film;

performing a second patterning to form a wiring layer;

forming an oxide semiconductor film, a second insulating film, and a third conductive layer over the first insulating film and the wiring layer;

performing a third patterning to form an island-shaped oxide semiconductor film, an island-shaped second insulating film over the island-shaped oxide semiconductor film, and a second gate electrode over the island-shaped second insulating film;

forming an interlayer insulating layer covering the first insulating film, the wiring layer, the island-shaped oxide semiconductor film, the island-shaped second insulating film, and the second gate electrode;

performing a fourth patterning to form an opening portion reaching the second gate electrode and an opening portion reaching the wiring layer;

forming a conductive material over the interlayer insulating layer; and

performing a fifth patterning to form a lead wiring connected to the second gate electrode and a pixel electrode connected to the wiring layer.

2. A method for manufacturing a semiconductor device comprising:

forming a first conductive layer over an insulating surface;

performing a first patterning to form a first gate electrode;

forming a first insulating film over the first gate electrode;

forming a second conductive layer over the first insulating film;

performing second patterning to form a wiring layer;

forming an oxide semiconductor film, a channel protective film, a second insulating film, and a third conductive layer over the first insulating film and the wiring layer;

performing a third patterning to form an island-shaped oxide semiconductor film, an island-shaped channel protective film over the island-shaped oxide semiconductor film, an island-shaped second insulating film over the island-shaped channel protective film, and a second gate electrode over the island-shaped second insulating film;

forming an interlayer insulating layer covering the first insulating film, the wiring layer, the island-shaped oxide semiconductor film, the island-shaped channel protective film, the island-shaped second insulating film, and the second gate electrode;

performing a fourth patterning to form an opening portion reaching the second gate electrode and an opening portion reaching the wiring layer;

forming a conductive material over the interlayer insulating layer; and

performing a fifth patterning to form a lead wiring connected to the second gate electrode and a pixel electrode connected to the wiring layer.

3. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the oxide semiconductor film is a first oxide semiconductor film,

wherein a second oxide semiconductor film is formed over the wiring layer by performing the second patterning, and

wherein a buffer layer formed from the second oxide semiconductor film is provided by performing the third patterning in a region where the oxide semiconductor film and the wiring layer overlap with each other.

4. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the oxide semiconductor film is a first oxide semiconductor film, and

wherein a second oxide semiconductor film is formed below the wiring layer by performing the second patterning.

5. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the lead wiring is provided to overlap with the second gate electrode.

6. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the interlayer insulating layer is formed using polyimide.

7. The method for manufacturing a semiconductor device according to claim 2 ,

wherein the channel protective film is formed using amorphous silicon.

8. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the oxide semiconductor film includes silicon oxide.

9. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the lead wiring is formed to be connected to the first gate electrode.

10. The method for manufacturing a semiconductor device according to claim 1 or claim 2 ,

wherein the second insulating film is formed to a thickness of from 50 nm to 500 nm inclusive.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2010
From: AKIMOTO, KENGO; KAWAE, DAISUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 024295/0599 →
Priority Claims (1)
JP 2009-111693 · May 1, 2009 · national
Continuity (1)
Related Publication 20100279474A1 · Nov 4, 2010