Thin film transistor with multiple oxide semiconductor layers
View Patent ↗A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.
1. A semiconductor device comprising:
a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a gate insulating layer over the third oxide semiconductor layer; and
a gate electrode over the gate insulating layer,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and comprises at least one of nitrogen, argon, and aluminum.
2. A semiconductor device comprising:
a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a first insulating layer over the third oxide semiconductor layer;
a gate electrode over the first insulating layer, and
a second insulating layer in contact with a side surface of the gate electrode,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and the second insulating layer and comprises at least one of nitrogen, argon, and aluminum.
3. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
4. The semiconductor device according to claim 2 , wherein the third oxide semiconductor layer is in contact with a side surface of the first oxide semiconductor layer and a side surface of the second oxide semiconductor layer.
5. The semiconductor device according to claim 3 ,
wherein the side surface of the first oxide semiconductor layer is tapered, and
wherein the side surface of the second oxide semiconductor layer is tapered.
6. The semiconductor device according to claim 4 ,
wherein the side surface of the first oxide semiconductor layer is tapered, and
wherein the side surface of the second oxide semiconductor layer is tapered.
7. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.
8. The semiconductor device according to claim 2 , wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer.
9. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.
10. The semiconductor device according to claim 2 , wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.
11. The semiconductor device according to claim 1 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.
12. The semiconductor device according to claim 2 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.
13. The semiconductor device according to claim 1 , further comprising:
a source electrode layer in contact with a first side surface of the first oxide semiconductor layer, a first side surface of the second oxide semiconductor layer, and a first side surface of the third oxide semiconductor layer; and
a drain electrode layer in contact with a second side surface of the first oxide semiconductor layer, a second side surface of the second oxide semiconductor layer, and a second side surface of the third oxide semiconductor layer.