IP Library › Granted Patent US 9,583,570
Granted Patent B2
US 9,583,570 · App. 14/813,408 · Granted Feb 28, 2017

Oxide semiconductor stacked film and semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Masashi Tsubuku (Atsugi, JP); Ryosuke Watanabe (Yamato, JP); Masashi Oota (Atsugi, JP); Noritaka Ishihara (Kawasaki, JP); Koki Inoue (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/1054H01L22/14H01L29/247H01L29/42356H01L29/42384H01L29/7869H01L29/78693H01L29/78696H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,583,570
App. No.
14/813,408
Granted
Feb 28, 2017
Kind
B2
Abstract

An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10 −3 /cm in an energy range of 1.5 eV to 2.3 eV.

Claims (71)

1. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;

a third oxide semiconductor layer over and in contact with the second oxide semiconductor layer;

a pair of electrode layers in contact with the third oxide semiconductor layer;

a gate electrode layer, wherein the gate electrode layer, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap each other; and

a gate insulating film between the gate electrode layer and the pair of electrode layers,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, gallium, and zinc,

wherein a conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than a conduction band of the second oxide semiconductor layer,

wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer,

wherein one of the pair of electrode layers and the gate electrode layer overlap each other, and

wherein the other of the pair of electrode layers and the gate electrode layer overlap each other.

2. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer comprises a crystal part.

3. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer further covers side surfaces of the first oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein an absorption coefficient of a channel formation region in an oxide semiconductor stacked film comprising the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer, which is measured by a CPM, is lower than or equal to 3×10 −3 /cm in an energy range of 1.5 eV to 2.3 eV.

5. The semiconductor device according to claim 1 , wherein energy at a bottom of the conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than energy at a bottom of the conduction band of the second oxide semiconductor layer.

6. The semiconductor device according to claim 1 , wherein in the second oxide semiconductor layer, a content percentage of indium is higher than a content percentage of gallium.

7. The semiconductor device according to claim 1 , wherein a content percentage of indium in the second oxide semiconductor layer is higher than a content percentage of indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer.

8. The semiconductor device according to claim 1 ,

wherein an atomic ratio of indium, gallium, and zinc in the first oxide semiconductor layer is 1:3:2,

wherein an atomic ratio of indium, gallium, and zinc in the second oxide semiconductor layer is 1:1:1, and

wherein an atomic ratio of indium, gallium, and zinc in the third oxide semiconductor layer is 1:3:2.

9. The semiconductor device according to claim 1 ,

wherein an atomic ratio of indium, gallium, and zinc in the first oxide semiconductor layer is 1:3:2,

wherein an atomic ratio of indium, gallium, and zinc in the second oxide semiconductor layer is 3:1:2, and

wherein an atomic ratio of indium, gallium, and zinc in the third oxide semiconductor layer is 1:1:1.

10. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;

a third oxide semiconductor layer over and in contact with the second oxide semiconductor layer;

a pair of electrode layers in contact with the third oxide semiconductor layer;

a gate electrode layer, wherein the gate electrode layer, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap each other; and

a gate insulating film between the gate electrode layer and the pair of electrode layers,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, gallium, and zinc,

wherein a conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than a conduction band of the second oxide semiconductor layer,

wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer,

wherein a conductivity of the second oxide semiconductor layer is higher than a conductivity of each of the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein one of the pair of electrode layers and the gate electrode layer overlap each other, and

wherein the other of the pair of electrode layers and the gate electrode layer overlap each other.

11. The semiconductor device according to claim 10 , wherein the second oxide semiconductor layer comprises a crystal part.

12. The semiconductor device according to claim 10 , wherein the third oxide semiconductor layer further covers side surfaces of the first oxide semiconductor layer.

13. The semiconductor device according to claim 10 , wherein an absorption coefficient of a channel formation region in an oxide semiconductor stacked film comprising the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer, which is measured by a CPM, is lower than or equal to 3×10 −3 /cm in an energy range of 1.5 eV to 2.3 eV.

14. The semiconductor device according to claim 10 , wherein energy at a bottom of the conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than energy at a bottom of the conduction band of the second oxide semiconductor layer.

15. The semiconductor device according to claim 10 , wherein in the second oxide semiconductor layer, a content percentage of indium is higher than a content percentage of gallium.

16. The semiconductor device according to claim 10 , wherein a content percentage of indium in the second oxide semiconductor layer is higher than a content percentage of indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer.

17. The semiconductor device according to claim 10 ,

wherein an atomic ratio of indium, gallium, and zinc in the first oxide semiconductor layer is 1:3:2,

wherein an atomic ratio of indium, gallium, and zinc in the second oxide semiconductor layer is 1:1:1, and

wherein an atomic ratio of indium, gallium, and zinc in the third oxide semiconductor layer is 1:3:2.

18. The semiconductor device according to claim 10 ,

wherein an atomic ratio of indium, gallium, and zinc in the first oxide semiconductor layer is 1:3:2,

wherein an atomic ratio of indium, gallium, and zinc in the second oxide semiconductor layer is 3:1:2, and

wherein an atomic ratio of indium, gallium, and zinc in the third oxide semiconductor layer is 1:1:1.

19. The semiconductor device according to claim 10 , wherein the conductivity of the second oxide semiconductor layer is higher than the conductivity of each of the first oxide semiconductor layer and the third oxide semiconductor layer by 1×10 3 S/cm or more.

20. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;

a third oxide semiconductor layer over and in contact with the second oxide semiconductor layer;

a pair of electrode layers in contact with the third oxide semiconductor layer;

a gate electrode layer, wherein the gate electrode layer, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer overlap each other; and

a gate insulating film between the gate electrode layer and the pair of electrode layers,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer,

wherein a content percentage of indium in the second oxide semiconductor layer is higher than a content percentage of indium in each of the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein one of the pair of electrode layers and the gate electrode layer overlap each other, and

wherein the other of the pair of electrode layers and the gate electrode layer overlap each other.

21. The semiconductor device according to claim 20 , wherein the second oxide semiconductor layer comprises a crystal part.

22. The semiconductor device according to claim 20 , wherein the third oxide semiconductor layer further covers side surfaces of the first oxide semiconductor layer.

23. The semiconductor device according to claim 20 , wherein an absorption coefficient of a channel formation region in an oxide semiconductor stacked film comprising the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer, which is measured by a CPM, is lower than or equal to 3×10 −3 /cm in an energy range of 1.5 eV to 2.3 eV.

24. The semiconductor device according to claim 20 , wherein energy at a bottom of the conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher than energy at a bottom of the conduction band of the second oxide semiconductor layer.

25. The semiconductor device according to claim 20 , wherein in the second oxide semiconductor layer, the content percentage of indium is higher than a content percentage of gallium.

Priority Claims (1)
JP 2012-173388 · Aug 3, 2012 · national
Continuity (3)
Continuation 14527076 · Oct 29, 2014
Continuation 13953428 · Jul 29, 2013
Related Publication 20150349133A1 · Dec 3, 2015