IP Library › Granted Patent US 9,059,219
Granted Patent B2
US 9,059,219 · App. 13/911,476 · Granted Jun 16, 2015

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shinya Sasagawa (Chigasaki, JP); Hiroshi Fujiki (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L29/66742H01L29/78648H01L29/7869H01L29/78696
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Quick Facts
Patent No.
US 9,059,219
App. No.
13/911,476
Granted
Jun 16, 2015
Kind
B2
Abstract

Provided is a method for manufacturing a transistor by which the defective shape of a semiconductor device is prevented in the case where a source electrode layer and a drain electrode layer are formed on an oxide semiconductor film. A source electrode layer and a drain electrode layer are formed each having a cross-sectional shape with which disconnection of a gate insulating film is unlikely to occur even when the gate insulating film over the source electrode layer and the drain electrode layer has a small thickness. An oxide semiconductor film having a crystal structure over an insulating surface is formed; an electrode layer on the oxide semiconductor film is formed; and a thickness of an exposed portion of the oxide semiconductor film is reduced by exposing the oxide semiconductor film to dilute hydrofluoric acid with a concentration higher than 0.0001% and lower than or equal to 0.25%.

Claims (57)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and

exposing a part of the oxide semiconductor layer to diluted hydrofluoric acid after the formation of the source electrode layer and the drain electrode layer,

wherein a concentration of the diluted hydrofluoric acid is higher than 0.0001% and lower than or equal to 0.25%.

2. The method according to claim 1 , wherein the oxide semiconductor layer has a crystal structure.

3. The method according to claim 1 , wherein the step of forming the oxide semiconductor layer comprises the steps of:

forming a first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer; and

forming a third oxide semiconductor layer over the second oxide semiconductor layer.

4. The method according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The method according to claim 1 , further comprising the step of:

forming a gate electrode layer before the formation of the oxide semiconductor layer.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

exposing a part of the oxide semiconductor layer to diluted hydrofluoric acid after the formation of the source electrode layer and the drain electrode layer;

forming an insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

forming a gate electrode layer over the insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer,

wherein a concentration of the diluted hydrofluoric acid is higher than 0.0001% and lower than or equal to 0.25%.

7. The method according to claim 6 , wherein the oxide semiconductor layer has a crystal structure.

8. The method according to claim 6 , wherein the step of forming the oxide semiconductor layer comprises the steps of:

forming a first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer; and

forming a third oxide semiconductor layer over the second oxide semiconductor layer.

9. The method according to claim 6 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. The method according to claim 6 , wherein the step of forming the gate electrode layer comprises the steps of:

forming a first gate electrode layer; and

forming a second gate electrode layer over the first gate electrode layer.

11. The method according to claim 6 , further comprising the step of:

forming a wiring electrically connected to one of the source electrode layer and the drain electrode layer,

wherein the wiring comprises copper.

12. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first electrode layer over an insulating surface;

forming a first insulating layer over the first electrode layer;

forming an oxide semiconductor layer over the first insulating layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

exposing a part of the oxide semiconductor layer to diluted hydrofluoric acid after the formation of the source electrode layer and the drain electrode layer;

forming a second insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

forming a second electrode layer over the second insulating layer, the second electrode layer overlapping with the oxide semiconductor layer,

wherein a concentration of the diluted hydrofluoric acid is higher than 0.0001% and lower than or equal to 0.25%.

13. The method according to claim 12 wherein the oxide semiconductor layer has a crystal structure.

14. The method according to claim 12 , wherein the step of forming the oxide semiconductor layer comprises the steps of:

forming a first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer; and

forming a third oxide semiconductor layer over the second oxide semiconductor layer.

15. The method according to claim 12 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

16. The method according to claim 12 , wherein the step of forming the second electrode layer comprises the steps of:

forming a first gate electrode layer; and

forming a second gate electrode layer over the first gate electrode layer.

17. The method according to claim 12 , further comprising the step of:

forming a wiring electrically connected to one of the source electrode layer and the drain electrode layer,

wherein the wiring comprises copper.

18. The method according to claim 12 , wherein the first electrode layer is a back gate electrode layer.

19. The method according to claim 12 , wherein the first electrode layer overlaps with the oxide semiconductor layer.

20. The method according to claim 12 , further comprising the step of:

adding oxygen to the first insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2013
From: SASAGAWA, SHINYA; FUJIKI, HIROSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030559/0966 →
Priority Claims (1)
JP 2012-144728 · Jun 27, 2012 · national
Continuity (1)
Related Publication 20140004656A1 · Jan 2, 2014