Stacked oxide material, semiconductor device, and method for manufacturing the semiconductor device
View Patent ↗One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.
1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode layer including a flat surface over a surface of a base;
forming a gate insulating layer over the gate electrode layer;
forming a first oxide semiconductor layer over the gate insulating layer;
causing crystal growth which proceeds from an upper surface toward an inside of the first oxide semiconductor layer by first heat treatment to form a first non-single crystalline layer;
forming a second oxide semiconductor layer over the first non-single crystalline layer;
causing crystal growth which proceeds from the first non-single crystalline layer toward an upper surface of the second oxide semiconductor layer over the first non-single crystalline layer by second heat treatment to form a second non-single crystalline layer; and
forming a source electrode layer and a drain electrode layer over a stack of the first non-single crystalline layer and the second non-single crystalline layer,
wherein a bottom interface whose crystal is aligned of the first non-single crystalline layer is provided to be spaced from a surface of the gate insulating layer.
2. The method for manufacturing a semiconductor device, according to claim 1 ,
wherein the first non-single crystalline layer is c-axis-aligned perpendicularly to a surface thereof.
3. The method for manufacturing a semiconductor device, according to claim 1 ,
wherein the second non-single crystalline layer is c-axis-aligned perpendicularly to a surface thereof.
4. The method for manufacturing a semiconductor device, according to claim 1 , wherein the second oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer.
5. A semiconductor device comprising:
a gate electrode layer including a flat surface over a surface of a base;
a gate insulating layer over the gate electrode layer;
a metal oxide layer including an amorphous region over the gate insulating layer;
a first non-single crystalline layer which is c-axis-aligned perpendicularly to a surface, over the metal oxide layer including the amorphous region;
a second non-single crystalline layer which is on and in contact with the first non-single crystalline layer and c-axis-aligned perpendicularly to the surface thereof; and
a source electrode and a drain electrode over a stack of the first non-single crystalline layer and the second non-single crystalline layer,
wherein the first non-single crystalline layer and the second non-single crystalline layer are metal oxide layers.
6. The semiconductor device according to claim 5 , wherein the second non-single crystalline layer has a larger thickness than the first non-single crystalline layer.
7. The semiconductor device according to claim 5 , wherein the first non-single crystalline layer and the second non-single crystalline layer have a same electron affinity.
8. The semiconductor device according to claim 5 , wherein the first non-single crystalline layer and the second non-single crystalline layer are formed using different materials.
9. The semiconductor device according to claim 5 , wherein a difference in height at a region in the surface of the second non-single crystalline layer which overlaps with the gate electrode layer is less than or equal to 1 nm.
10. The semiconductor device according to claim 5 , wherein a difference in height at a region in the surface of the second non-single crystalline layer which overlaps with the gate electrode layer is less than or equal to 0.2 nm.
11. The method for manufacturing a semiconductor device, according to claim 1 ,
wherein the first oxide semiconductor layer is formed by a sputtering method using a first metal oxide target,
wherein the second oxide semiconductor layer is formed by a sputtering method using a second metal oxide target,
wherein each of the first metal oxide target and the second metal oxide target contains indium, gallium and zinc, and
wherein composition ratio of the first metal oxide target is different from the composition ratio of the second metal oxide target.