IP Library › Granted Patent US 8,987,731
Granted Patent B2
US 8,987,731 · App. 13/895,577 · Granted Mar 24, 2015

Semiconductor device and method for manufacturing the same

Inventor: Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78693H01L29/7869
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Quick Facts
Patent No.
US 8,987,731
App. No.
13/895,577
Granted
Mar 24, 2015
Kind
B2
Abstract

In order to form a structure in which an oxide semiconductor layer through which a carrier flows is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which a carrier flows is away from the gate insulating film containing silicon is provided. Specifically, a buffer layer is provided between the gate insulating film and the oxide semiconductor layer. Both the oxide semiconductor layer and the buffer layer are formed using materials containing indium and another metal element. The composition of indium with respect to gallium contained in the oxide semiconductor layer is higher than the composition of indium with respect to gallium contained in the buffer layer. The buffer layer has a smaller thickness than the oxide semiconductor layer.

Claims (57)

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a third oxide semiconductor layer over the second oxide semiconductor layer,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least indium and a metal element,

wherein a composition of indium with respect to the metal element in the first oxide semiconductor layer is different from a composition of indium with respect to the metal element in the second oxide semiconductor layer, and

wherein a side surface of the gate insulating layer and a side surface of the first oxide semiconductor layer are substantially aligned with each other.

2. The semiconductor device according to claim 1 , wherein the metal element is gallium.

3. The semiconductor device according to claim 2 ,

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the first oxide semiconductor layer.

4. The semiconductor device according to claim 1 , further comprising

a second gate electrode over the third oxide semiconductor layer.

5. The semiconductor device according to claim 1 , further comprising an insulating layer over and in contact with the third oxide semiconductor layer,

wherein the insulating layer comprises silicon.

6. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a third oxide semiconductor layer over the second oxide semiconductor layer,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least indium and a metal element,

wherein a composition of indium with respect to the metal element in the first oxide semiconductor layer is different from a composition of indium with respect to the metal element in the second oxide semiconductor layer,

wherein a composition of indium with respect to the metal element in the third oxide semiconductor layer is different from a composition of indium with respect to the metal element in the second oxide semiconductor layer, and

wherein a side surface of the gate insulating layer and a side surface of the first oxide semiconductor layer are substantially aligned with each other.

7. The semiconductor device according to claim 6 , wherein the metal element is gallium.

8. The semiconductor device according to claim 7 ,

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the first oxide semiconductor layer.

9. The semiconductor device according to claim 7 ,

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the first oxide semiconductor layer, and

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the third oxide semiconductor layer.

10. The semiconductor device according to claim 6 , further comprising

a second gate electrode over the third oxide semiconductor layer.

11. The semiconductor device according to claim 6 , further comprising an insulating layer over and in contact with the third oxide semiconductor layer,

wherein the insulating layer comprises silicon.

12. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a third oxide semiconductor layer over the second oxide semiconductor layer,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least indium and a metal element,

wherein a composition of indium with respect to the metal element in the first oxide semiconductor layer is different from a composition of indium with respect to the metal element in the second oxide semiconductor layer,

wherein a composition of indium with respect to the metal element in the third oxide semiconductor layer is different from a composition of indium with respect to the metal element in the second oxide semiconductor layer,

wherein a thickness of the second oxide semiconductor layer is larger than a thickness of the first oxide semiconductor layer and a thickness of the third oxide semiconductor layer, and

wherein a side surface of the gate insulating layer and a side surface of the first oxide semiconductor layer are substantially aligned with each other.

13. The semiconductor device according to claim 12 , wherein the metal element is gallium.

14. The semiconductor device according to claim 13 ,

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the first oxide semiconductor layer.

15. The semiconductor device according to claim 13 ,

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the first oxide semiconductor layer, and

wherein a composition of indium with respect to gallium in the second oxide semiconductor layer is higher than a composition of indium with respect to gallium in the third oxide semiconductor layer.

16. The semiconductor device according to claim 12 , further comprising

a second gate electrode over the third oxide semiconductor layer.

17. The semiconductor device according to claim 12 , further comprising an insulating layer over and in contact with the third oxide semiconductor layer,

wherein the insulating layer comprises silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2013
From: YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030431/0332 →
Priority Claims (1)
JP 2012-125394 · May 31, 2012 · national
Continuity (1)
Related Publication 20130320330A1 · Dec 5, 2013