IP Library Granted Patent US 10,090,585
Granted Patent B2
US 10,090,585 · App. 15/244,869 · Granted Oct 2, 2018

Circuits and methods for antenna-based self-interference cancellation

Inventors: Tolga Dinc (New York, NY); Harish Krishnaswamy (New York, NY)
Assignee: The Trustees of Columbia University in the City of New York
H01Q1/38H01Q1/525H01Q5/314H01Q21/06H04B1/06H04W16/14
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Quick Facts
Patent No.
US 10,090,585
App. No.
15/244,869
Granted
Oct 2, 2018
Kind
B2
Abstract

Circuits and methods for antenna-based self-interference cancellation are provided. In some embodiments, circuits for antenna-based self-interference cancellation are provided, the circuits comprising: a transmit antenna having a transmit port that receives a transmit signal; a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port.

Claims (11)

1. A circuit for antenna-based self-interference cancellation, comprising:

a transmit antenna having a transmit port that receives a transmit signal;

a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and

a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port.

2. The circuit of claim 1 , wherein the termination is formed from a parallel combination of a resistance, an inductance, and a capacitance.

3. The circuit of claim 2 , wherein the inductance is fixed.

4. The circuit of claim 3 , wherein the inductance is implemented using a transmission line.

5. The circuit of claim 2 , wherein the resistance is implemented using a voltage controlled attenuator.

6. The circuit of claim 2 , wherein the capacitance is implemented using a varactor diode.

7. The circuit of claim 1 , wherein the transmit port, the receive port, and the auxiliary port each have non-zero feed line length.

8. The circuit of claim 1 , wherein a slope of conductance synthesized by the termination over a frequency range is substantially zero.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2017
From: DINC, TOLGA; KRISHNASWAMY, HARISH
To: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
Reel/Frame 042951/0534 →
CONFIRMATORY LICENSE Recorded Nov 17, 2016
From: COLUMBIA UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 040634/0513 →
Continuity (2)
Provisional Application 62208803 · Aug 23, 2015
Related Publication 20170054224A1 · Feb 23, 2017
Cited By (10)
US 12,237,811 US 12,332,376 US 12,386,029 US 12,386,030 US 12,429,555 US 12,461,219 US 12,498,452 US 12,650,503 US 12,674,865 US 12,681,135