Power Driven Optimization For Flash Memory
A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and perform the same operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin. The operations of varying energy margins are based on the required storage longevity of the data being stored (lower energy margins for data being stored for shorter periods of time) to save energy and wear.
1 . A memory device, comprising:
an array of non-volatile memory cells; and
a controller configured to:
perform an operation on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and
perform the operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin.
2 . The device of claim 1 , wherein the operation is programming.
3 . The device of claim 1 , wherein the operation is erasing.
4 . The device of claim 1 , wherein the operation is reading.
5 . The device of claim 1 , further comprising:
a charge pump for generating the operational voltages for performing the operation on the first plurality of the non-volatile memory cells, and for generating the operational voltages for performing the operation on the second plurality of the non-volatile memory cells.
6 . The device of claim 2 , the controller is further configured to:
determine a first data to be programmed to the first plurality of non-volatile memory cells is associated with a storage longevity that is less than a storage longevity associated with a second data to be programmed to the second plurality of non-volatile memory cells; and
utilize the first energy margin for performing the operation on the first plurality of non-volatile memory cells and utilize the second energy margin for performing the operation on the second plurality of non-volatile memory cells based upon the determination.
7 . The device of claim 1 , wherein the controller is further configured to:
utilize the first energy margin for performing the operation on the first plurality of non-volatile memory cells and utilize the second energy margin for performing the operation on the second plurality of non-volatile memory cells in response to a received signal.
8 . The device of claim 1 , wherein at least one of a voltage, a current, a time duration, and a number of pulses of the operational voltages for performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages for performing the operation on the first plurality of non-volatile memory cells.
9 . The device of claim 1 , wherein at least one voltage of the operational voltages for performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages for performing the operation on the first plurality of non-volatile memory cells.
10 . The device of claim 1 , wherein at least one current of the operational voltages for performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages for performing the operation on the first plurality of non-volatile memory cells.
11 . The device of claim 1 , wherein at least one time duration of the operational voltages for performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages for performing the operation on the first plurality of non-volatile memory cells.
12 . The device of claim 1 , wherein a number of pulses of the operational voltages for performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages for performing the operation on the first plurality of non-volatile memory cells.
13 . A method of operating a memory device having an array of non-volatile memory cells, comprising:
performing an operation on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and
performing the operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin.
14 . The method of claim 13 , wherein the operation is programming.
15 . The method of claim 13 , wherein the operation is erasing.
16 . The method of claim 13 , wherein the operation is reading.
17 . The method of claim 14 , further comprising:
determining a first data to be programmed to the first plurality of non-volatile memory cells is associated with a storage longevity that is less than a storage longevity associated with a second data to be programmed to the second plurality of non-volatile memory cells;
wherein the performing of the operation on the first plurality of non-volatile memory cells using the first energy margin and the performing of the operation on the second plurality of non-volatile memory cells using the second energy margin is based upon the determining.
18 . The method of claim 13 , wherein the performing of the operation on the first plurality of non-volatile memory cells using the first energy margin and the performing of the operation on the second plurality of non-volatile memory cells using the second energy margin is in response to a received signal.
19 . The method of claim 13 , wherein at least one of a voltage, a current, a time duration, and a number of pulses of the operational voltages in performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages in performing the operation on the first plurality of non-volatile memory cells.
20 . The method of claim 13 , wherein at least one voltage of the operational voltages in performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages in performing the operation on the first plurality of non-volatile memory cells.
21 . The method of claim 13 , wherein at least one current of the operational voltages in performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages in performing the operation on the first plurality of non-volatile memory cells.
22 . The method of claim 13 , wherein at least one time duration of the operational voltages in performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages in performing the operation on the first plurality of non-volatile memory cells.
23 . The method of claim 13 , wherein a number of pulses of the operational voltages in performing the operation on the second plurality of non-volatile memory cells is greater than that of the operational voltages in performing the operation on the first plurality of non-volatile memory cells.