IP Library Granted Patent US 10,250,207
Granted Patent B2
US 10,250,207 · App. 15/251,955 · Granted Apr 2, 2019

Method and system for a feedback transimpedance amplifier with sub-40KHZ low-frequency cutoff

Inventor: Brian Welch (San Diego, CA)
Assignee: Luxtera, Inc.
H03F3/45237G01J1/44H03F1/34H03F3/087H03F3/45071H03F3/45076H03F3/45475H03F3/45968H03F2200/405H03F2203/45222H03F2203/45288H03F2203/45511H03F2203/45526
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,250,207
App. No.
15/251,955
Granted
Apr 2, 2019
Kind
B2
Abstract

A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.

Claims (29)

1. A system for processing electrical signals, the system comprising:

an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source followers and feedback resistors, wherein:

said feedback paths are coupled to first terminals of said coupling capacitors;

second terminals of said coupling capacitors are coupled to inputs of said gain stage;

said gain stage amplifies electrical signals received via said coupling capacitors; and

gate terminals of said source followers are coupled to output terminals of said gain stage.

2. The system according to claim 1 , wherein said source followers are operable to level shift voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.

3. The system according to claim 1 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.

4. The system according to claim 3 , wherein said CMOS chip comprises a CMOS photonics chip.

5. The system according to claim 4 , wherein said CMOS photonics chip receives optical signals for said photodetector via one or more optical fibers.

6. The system according to claim 1 , wherein said source followers comprise CMOS transistors.

7. The system according to claim 1 , wherein said gain stage receives current-mode logic signals.

8. The system according to claim 1 , wherein said gain stage receives voltage signals.

9. The system according to claim 1 , wherein said electrical signals are received from a photodetector.

10. The system according to claim 9 , wherein said photodetector comprises a silicon germanium photodiode.

11. The system according to claim 9 , wherein said photodetector is differentially coupled to said gain stage.

12. A method for processing optical signals, the method comprising:

in an amplifier circuit having coupling capacitors, a gain stage, and feedback paths comprising source followers and feedback resistors, wherein said feedback paths are coupled to first terminals of said coupling capacitors, second terminals of said coupling capacitors are coupled to inputs of said gain stage, and gate terminals of said source followers are coupled to output terminals of said gain stage:

amplifying electrical signals received via said coupling capacitors utilizing said gain stage.

13. The method according to claim 12 , comprising level shifting voltages prior to said coupling capacitors to ensure stable bias conditions for said amplifier circuit.

14. The method according to claim 12 , wherein said source followers comprise CMOS transistors.

15. The method according to claim 12 , wherein said gain stage receives current-mode logic signals.

16. The method according to claim 12 , wherein said gain stage received voltage signals.

17. The method according to claim 12 , wherein said amplifier circuit is integrated in a complementary metal-oxide semiconductor (CMOS) chip.

18. The method according to claim 17 , wherein said CMOS chip comprises a CMOS photonics chip.

19. The method according to claim 12 , comprising receiving said electrical signals from a photodetector.

20. The method according to claim 19 , comprising receiving optical signals for said photodetector in said CMOS photonics chip via one or more optical fibers.

21. The method according to claim 19 , wherein said photodetector comprises a silicon germanium photodiode.

22. The method according to claim 19 , wherein said photodetector is differentially coupled to said gain stage.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2018
From: WELCH, BRIAN
To: LUXTERA, INC.
Reel/Frame 045739/0715 →
Continuity (5)
Continuation 14305733 · Jun 16, 2014
Continuation 13926851 · Jun 25, 2013
Continuation 13175545 · Jul 1, 2011
Provisional Application 61398987 · Jul 6, 2010
Related Publication 20160373078A1 · Dec 22, 2016
Cited By (2)
US 12,191,915 US 12,542,517