Multi-type parity bit generation for encoding and decoding

1. A memory system comprising:

memory; and

a controller configured to:

generate a codeword comprising a plurality of information bits, a plurality of first-type parity bits, and a second-type parity bit;

identify a storage location of the memory in which to store the codeword, wherein the storage location comprises a bad memory cell, and wherein an information bit or a first-type parity bit is mapped to the bad memory cell;

re-map the codeword so that the second-type parity bit is mapped to the bad memory cell; and

store the codeword in the storage location such that the second-type parity bit is stored in the bad memory cell.

2. The memory system of claim 1 , wherein the controller is configured to encode the information bits by individually encoding a plurality of portions of the information bits, wherein the plurality of first-type parity bits comprises a plurality of sub-code parity bits and the second-type parity bit comprises a joint parity bit.

3. The memory system of claim 1 , wherein the controller is configured to encode the plurality of information bits with a parity-check matrix comprising a number of columns and a number of rows, each corresponding to a number of one or more second-type parity bits of the codeword comprising the second-type parity bit.

4. The memory system of claim 3 , wherein elements of the parity-check matrix that are in both the number of columns and the number of rows corresponding to the number of the one or more second-type parity bits form a lower triangular submatrix of the parity-check matrix.

5. The memory system of claim 3 , wherein the number of rows corresponding to the number of the one or more second-type parity bits comprises a first number of rows of the parity-check matrix, the parity-check matrix further comprising a second number of rows corresponding to the first-type parity bits, and wherein elements of the parity-check matrix that are in the number of columns corresponding to the one or more second-type parity bits and in the second number of rows corresponding to the first-type parity bits are all zeros.

6. The memory system of claim 3 , wherein the number of columns and the number of rows corresponding to the number of the one or more second-type parity bits corresponds to a number of replacement columns for a page of the memory.

7. A method of storing data, the method comprising:

determining, with a controller of a memory system, to store data in a storage location of the memory system;

identifying, with the controller, a bad memory cell of the storage location;

before storing a codeword associated with the data in the storage location, changing, with the controller, which bit of the codeword is to be stored in the bad memory cell; and

storing the codeword in the storage location based on the changing.

8. The method of claim 7 , wherein changing which bit comprises switching the bad memory cell from being mapped to an information bit or a first-type parity bit of the codeword to a second-type parity bit of the codeword.

9. The method of claim 7 , wherein a number of second-type parity bits corresponds to a number of replacement columns associated with a page of the memory.

10. The method system of claim 7 , wherein a number of second-type parity bits corresponds to a predetermined maximum number of expected bad memory cells.

11. The method of claim 7 , further comprising:

generating, with the controller, the codeword to comprise a plurality of information bits, a plurality of sub-code parity bits, and one more joint parity bits.

12. The method of claim 7 , further comprising:

encoding, with the controller, a plurality of information bits with a parity-check matrix to generate the codeword, the parity-check matrix comprising a number of columns and a number of rows, each corresponding to a number of one or more second-type parity bits of the codeword.

13. The method of claim 12 , wherein elements of the parity-check matrix that are in both the number of columns and the number of rows corresponding to the one or more second-type parity bits form a lower triangular submatrix of the parity-check matrix.

14. The method of claim 12 , wherein the number of rows corresponding to the number of the one or more second-type parity bits comprises a first number of rows of the parity-check matrix, the parity-check matrix further comprising a second number of rows corresponding to the first-type parity bits, and wherein elements of the parity-check matrix that are in the number of columns corresponding to the one or more second-type parity bits and in the second number of rows corresponding to the first-type parity bits are all zeros.

15. A memory system comprising:

memory; and

a controller configured to:

generate a codeword comprising a plurality of information bits and a plurality of parity bits;

determine to store the codeword in a storage location of the memory comprising a bad memory cell;

before storing the codeword, re-map the codeword to change which bit of the codeword is stored in the bad memory cell; and

store the codeword in the storage location according to the re-mapping.

16. The memory system of claim 15 , wherein the controller is configured to switch the bad memory cell from being mapped to an information bit or a first-type parity bit of the codeword to a second-type parity bit of the codeword in order to re-map the codeword.

17. The memory system of claim 15 , wherein the plurality of parity bits comprises a plurality of first-type parity bits and one or more second-type parity bits, wherein a number of the one or more second-type parity bits corresponds to a number of replacement columns associated with a page of the memory.

18. The memory system of claim 15 , wherein the plurality of parity bits comprises a plurality of first-type parity bits and one or more second-type parity bits, wherein a number of the one second-type parity bits corresponds to a predetermined maximum number of expected bad memory cells.

19. The memory system of claim 15 , wherein the controller is further configured to encode the plurality of information bits with a parity-check matrix to generate the codeword, the parity-check matrix comprising a number of columns and a number of rows, each corresponding to a number of one or more second-type parity bits of the codeword.

20. The method of claim 19 , wherein elements of the parity-check matrix that are in both the number of columns and the number of rows corresponding to the one or more second-type parity bits form a lower triangular submatrix of the parity-check matrix.

21. The method of claim 19 , wherein the number of rows corresponding to the number of the one or more second-type parity bits comprises a first number of rows of the parity-check matrix, the parity-check matrix further comprising a second number of rows corresponding to the first-type parity bits, and wherein elements of the parity-check matrix that are in the number of columns corresponding to the one or more second-type parity bits and in the second number of rows corresponding to the first-type parity bits are all zeros.

22. A memory system comprising:

a memory; and

means for generating a codeword comprising a plurality of information bits, a plurality of first-type parity bits, and a second-type parity bit;

means for identifying a storage location of the memory in which to store the codeword, wherein the storage location comprises a bad memory cell, and wherein an information bit or a first-type parity bit is mapped to the bad memory cell;

means for re-mapping the codeword so that the second-type parity bit is mapped to the bad memory cell; and

means for storing the codeword in the storage location such that the second-type parity bit is stored in the bad memory cell.