Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
1. A integrated circuit device, comprising:
a fin including silicon;
a gate electrode over a portion of the fin; and
a source region and a drain region, the portion of the fin between the source and drain regions, each of the source and drain regions having a total thickness comprising a p-type liner of one or both of silicon or germanium and a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the p-type liner is less than 50% of the total thickness, and wherein the p-type liner is between the p-type cap and the portion of the fin, and wherein the p-type cap of each of the source and the drain regions includes one or more dislocations, the one or more dislocations including at least one of a misfit dislocation or a threading dislocation.
2. The device of claim 1 wherein the portion of the fin includes one or more nanowires.
3. The device of claim 1 further comprising metal-germanide source and drain contacts over the p-type caps.
4. The device of claim 1 wherein the thickness ratio of liner thickness to cap thickness is 2:5, or less.
5. The device of claim 1 wherein the portion of the fin is also between portions of the gate electrode.
6. The device of claim 1 wherein each of the liners has a thickness in the range of about one monolayer to 10 nm, and each of the caps has a thickness in the range of about 50 nm to 500 nm.
7. The device of claim 1 wherein at least one of the liners or caps has at least one of a graded concentration of germanium or p-type dopant.
8. The device of claim 7 wherein at least one of the liners has a germanium concentration that is graded from a base level concentration compatible with the portion of the fin to a high concentration in excess of 50 atomic %.
9. The device of claim 8 wherein the high concentration is in excess of 90 atomic %.
10. The device of claim 7 wherein at least one of the liners has a p-type dopant concentration that is graded from a base level concentration compatible with the portion of the fin to a high concentration in excess of 1E20 cm −3 .
11. The device of claim 10 wherein the p-dopant of the at least one of the liners is boron.
12. The device of claim 7 wherein at least one of the caps has a germanium concentration in excess of 95 atomic %.
13. The device of claim 7 wherein at least one of the caps has a germanium concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 80 atomic %.
14. The device of claim 7 wherein at least one of the caps has a p-type dopant concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 1E20 cm −3 .
15. The device of claim 14 wherein the p-dopant of the at least one of the caps is boron.
16. The device of claim 1 wherein at least one of the caps further comprises tin.
17. An integrated circuit, comprising:
a fin including silicon;
a gate electrode over a portion of the fin; and
a source region and a drain region, the portion of the fin between the source and drain regions, each of the source and drain regions comprising one or more nanowires, each nanowire including a bi-layer construction having a total thickness comprising a p-type liner of one or both of silicon or germanium and a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 40% of the total thickness, and wherein the p-type liner is between the p-type cap and the portion of the fin, and wherein the p-type cap of each of the source and drain regions includes one or more dislocations, the one or more dislocations including at least one of a misfit dislocation or a threading dislocation, and wherein the portion of the fin includes compressive strain.
18. The circuit of claim 17 wherein the thickness ratio of liner thickness to cap thickness is 1:5, or less.
19. The circuit of claim 17 wherein at least one of the caps further comprises tin in a concentration of 20% or less.
20. The circuit of claim 17 further comprising metal-germanide source and drain contacts over the p-type caps.